公开(公告)号：US07713465B2

公开(公告)日：2010-05-11

申请号：US12053082

申请日：2008-03-21

申请人： Shenglei Che ,  Kentaro Mori ,  Masahiko Watanabe ,  Takuya Aoki ,  Tomofumi Kuroda

发明人： Shenglei Che ,  Kentaro Mori ,  Masahiko Watanabe ,  Takuya Aoki ,  Tomofumi Kuroda

IPC分类号： C04B33/32

CPC分类号： H01F1/344 ,  C01G49/0018 ,  C01G49/009 ,  C01G53/006 ,  C01P2002/52 ,  C01P2006/80 ,  C04B35/265 ,  C04B35/6262 ,  C04B35/62695 ,  C04B2235/3203 ,  C04B2235/3208 ,  C04B2235/3239 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3262 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/3418 ,  C04B2235/5427 ,  C04B2235/656 ,  C04B2235/6562 ,  C04B2235/6565 ,  C04B2235/6584

摘要： Provided is a process for producing a MnZn-base ferrite comprising: firing a compacted raw material to produce the MnZn-base ferrite, wherein the firing comprises, in the following order: a heating phase comprising gradually bringing a firing temperature from room temperature up to a maximum temperature; a maximum temperature holding phase comprising maintaining the maximum temperature for a period of time, wherein a partial pressure of oxygen (p2) at the maximum temperature holding phase is greater than an equilibrium partial pressure of oxygen (p1) as follows: p2>p1, wherein the equilibrium partial pressure of oxygen (p1) is represented by the following equation: log(p1)=log(PO2)=a−b/T, wherein PO2 is measured in a unit of %, and T is measured in a unit of absolute temperature K; and a cooling phase comprising gradually bringing the maximum temperature down to near room temperature, wherein a partial pressure of oxygen (p3) at the cooling phase is operated at an equilibrium partial pressure of oxygen based on the equation log(p3)=a−b/T.

摘要翻译： 提供了一种MnZn基铁素体的制造方法，其特征在于，包括：烧结压实的原料以制造所述MnZn基铁氧体，其中所述烧制按以下顺序包括：加热阶段，包括逐渐使焙烧温度从室温升至 最高温度; 最大温度保持阶段包括将最高温度保持一段时间，其中在最高温度保持阶段的氧分压（p2）大于氧的平衡分压（p1），如下：p2> p1， 其中氧的平衡分压（p1）由以下等式表示：log（p1）= log（PO2）= a-b / T，其中PO2以％为单位测量，T以单位测量 绝对温度K; 和冷却阶段，其包括使最高温度逐渐降至接近室温，其中在冷却阶段的氧（p3）分压基于等式log（p3）= a-b在氧的平衡分压下操作 / T。

公开(公告)号：US08282853B2

公开(公告)日：2012-10-09

申请号：US12564483

申请日：2009-09-22

申请人： Kentaro Mori ,  Takuya Aoki

发明人： Kentaro Mori ,  Takuya Aoki

IPC分类号： H01F1/34

CPC分类号： H01F1/344 ,  C04B35/265 ,  C04B35/62685 ,  C04B2235/3208 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3263 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3418 ,  C04B2235/656 ,  C04B2235/77 ,  C04B2235/786 ,  H01F1/36 ,  H01F41/0246

摘要： A novel NiMnZn-based ferrite which can reduce magnetic loss (core loss) at a high frequency of about 2 MHz or higher and achieve higher saturated magnetic flux density while forming high sintered density is provided. The NiMnZn-based ferrite contains a main component comprising 54.0 to 57.5 mol % of iron oxide in terms of Fe2O3, 2.0 to 7.0 mol % of zinc oxide in terms of ZnO, 0.5 to 4.7 mol % of nickel oxide in terms of NiO, and a remainder of manganese oxide (in terms of MnO); and an accessory component comprising 100 to 1000 ppm by weight of Si in terms of SiO2, 800 to 3000 ppm by weight of Ca in terms of CaCO3, and 520 to 1000 ppm by weight of Nb in terms of Nb2O5 with respect to the main component; while having an average ferrite crystal particle size of 2.1 to 8.5 μm.

摘要翻译： 提供了一种新型的基于NiMnZn的铁氧体，其可以在形成高烧结密度的同时，在大约2MHz或更高的高频下降低磁损耗（磁芯损耗）并获得更高的饱和磁通密度。 NiMnZn系铁氧体含有以Fe2O3为54.0〜57.5摩尔％的氧化铁，以ZnO为2.0〜7.0摩尔％的氧化锌，NiO为0.5〜4.7摩尔％的氧化镍的主成分，以及 剩余的氧化锰（以MnO计）; 以及以SiO 2为100〜1000ppm的Si，以CaCO 3计为800〜3000质量ppm的Ca，相对于主成分为Nb 2 O 5的Nb为520〜1000质量ppm的Nb ; 而平均铁素体晶粒度为2.1〜8.5μm。

公开(公告)号：US20100078587A1

公开(公告)日：2010-04-01

申请号：US12564483

申请日：2009-09-22

申请人： Kentaro Mori ,  Takuya Aoki

发明人： Kentaro Mori ,  Takuya Aoki

IPC分类号： H01F1/01

CPC分类号： H01F1/344 ,  C04B35/265 ,  C04B35/62685 ,  C04B2235/3208 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3263 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3418 ,  C04B2235/656 ,  C04B2235/77 ,  C04B2235/786 ,  H01F1/36 ,  H01F41/0246

摘要： A novel NiMnZn-based ferrite which can reduce magnetic loss (core loss) at a high frequency of about 2 MHz or higher and achieve higher saturated magnetic flux density while forming high sintered density is provided. The NiMnZn-based ferrite contains a main component comprising 54.0 to 57.5 mol % of iron oxide in terms of Fe2O3, 2.0 to 7.0 mol % of zinc oxide in terms of ZnO, 0.5 to 4.7 mol % of nickel oxide in terms of NiO, and a remainder of manganese oxide (in terms of MnO); and an accessory component comprising 100 to 1000 ppm by weight of Si in terms of SiO2, 800 to 3000 ppm by weight of Ca in terms of CaCO3, and 520 to 1000 ppm by weight of Nb in terms of Nb2O5 with respect to the main component; while having an average ferrite crystal particle size of 2.1 to 8.5 μm.

摘要翻译： 提供了一种新型的基于NiMnZn的铁氧体，其可以在形成高烧结密度的同时，在大约2MHz或更高的高频下降低磁损耗（磁芯损耗）并获得更高的饱和磁通密度。 NiMnZn系铁氧体含有以Fe2O3为54.0〜57.5摩尔％的氧化铁，以ZnO为2.0〜7.0摩尔％的氧化锌，NiO为0.5〜4.7摩尔％的氧化镍的主成分，以及 剩余的氧化锰（以MnO计）; 以及以SiO 2为100〜1000ppm的Si，以CaCO 3计为800〜3000质量ppm的Ca，相对于主成分为Nb 2 O 5的Nb为520〜1000质量ppm的Nb ; 而平均铁素体晶粒度为2.1〜8.5μm。

公开(公告)号：US08975150B2

公开(公告)日：2015-03-10

申请号：US13190052

申请日：2011-07-25

申请人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

发明人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

IPC分类号： H01L21/76 ,  H01L21/683 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00

CPC分类号： H01L21/6835 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L2221/68345 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  Y10S438/977 ,  H01L2924/00

摘要： A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

摘要翻译： 透明板位于设置有定位标记的支撑板上，并且设置有释放材料。 然后将半导体元件定位成使得电极元件面向上，然后移除支撑板。 然后在剥离材料上形成绝缘树脂以覆盖半导体元件; 然后形成通孔，布线层，绝缘层，外部端子和阻焊剂。 然后透明板通过使用释放材料从半导体器件剥离。 因此，可以高精度地安装芯片，在制造过程中不需要在将芯片安装在基板上时提供定位标记，并且可以容易地去除基板。 结果，可以以低成本制造具有高密度和薄型的半导体器件。

公开(公告)号：US08827435B2

公开(公告)日：2014-09-09

申请号：US13325658

申请日：2011-12-14

申请人： Daisuke Uematsu ,  Kentaro Mori ,  Nobuhiro Hayakawa

发明人： Daisuke Uematsu ,  Kentaro Mori ,  Nobuhiro Hayakawa

IPC分类号： C09D11/00 ,  C09D7/12

CPC分类号： C09D11/322 ,  C09D7/67 ,  C09D7/68 ,  C09D11/52

摘要： There is provided an ink for printing a conductor pattern on a substrate, including platinum particles, wherein 70% or more of the platinum particles have a particle size of 0.05 to 0.5 μm. Even when the viscosity of the printing ink is controlled to a relatively low level for use in ink-jet printing process, it is possible by such particle size distribution control to prevent sedimentation of the platinum particles and excessive shrinkage of the conductor pattern due to sintering of the platinum particles during firing so that the conductor pattern can attain improved conduction characteristics.

摘要翻译： 提供了一种用于在包括铂颗粒的基板上印刷导体图案的油墨，其中70％或更多的铂颗粒具有0.05至0.5μm的粒径。 即使将印刷油墨的粘度控制在用于喷墨印刷工艺的较低水平，也可以通过这种粒度分布控制来防止铂颗粒的沉淀和由于烧结导致的导体图案的过度收缩 的铂粒子，使得导体图案可以获得改善的导电特性。

公开(公告)号：US08766440B2

公开(公告)日：2014-07-01

申请号：US13582128

申请日：2011-01-25

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

IPC分类号： H01L23/52

CPC分类号： H05K1/186 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H05K3/4644 ,  H01L2924/00

摘要： A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

摘要翻译： 包括内置半导体元件的布线板包括半导体元件，覆盖半导体元件的外周侧表面的外围绝缘层，设置在布线基板的上表面侧的上表面侧布线，以及下部 设置在布线基板的下表面侧的表面侧配线。 半导体元件包括：第一布线结构层，包括交替设置在半导体基板上的第一布线和第一绝缘层;以及第二布线结构层，包括交替设置在第一布线结构层上的第二布线和第二绝缘层。 上表面侧布线包括经由第二布线电连接到第一布线的布线。 第二布线比第一布线厚，比上表面布线薄。 第二绝缘层由树脂材料形成，并且比第一绝缘层厚。

公开(公告)号：US08710669B2

公开(公告)日：2014-04-29

申请号：US13320798

申请日：2010-05-18

申请人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00

摘要： A semiconductor device includes a core substrate, and at least one insulating layer and at least one wiring layer that are disposed on a first surface and a second, opposite surface of the substrate. The semiconductor device includes a via disposed in the insulating layer and in the core substrate, and which connects the wiring layers to one another. The semiconductor device includes a semiconductor element mounted on the first surface, forming an electrode terminal that faces up. The semiconductor device includes a connecting portion that penetrates the insulating layer and directly connects the electrode terminal of the semiconductor element and the wiring layer on the first surface. A minimum wiring pitch of this wiring that of any wiring layer on the second surface.

摘要翻译： 半导体器件包括芯基板，以及设置在基板的第一表面和第二相对表面上的至少一个绝缘层和至少一个布线层。 半导体器件包括布置在绝缘层和芯基板中并且将布线层彼此连接的通孔。 半导体器件包括安装在第一表面上的半导体元件，形成面向上的电极端子。 半导体器件包括穿透绝缘层并直接连接半导体元件的电极端子和第一表面上的布线层的连接部分。 该布线的最小布线间距为第二面上任何布线层的布线间距。

公开(公告)号：US20130272485A1

公开(公告)日：2013-10-17

申请号：US13992999

申请日：2011-12-06

申请人： Hiroshi Shimizu ,  Ryo Fujimoto ,  Kentaro Mori ,  Hiromu Okamoto ,  Hisashi Sekimoto ,  Hiroyuki Iseki

发明人： Hiroshi Shimizu ,  Ryo Fujimoto ,  Kentaro Mori ,  Hiromu Okamoto ,  Hisashi Sekimoto ,  Hiroyuki Iseki

IPC分类号： G21C13/024 ,  E04B1/16

CPC分类号： G21C13/024 ,  E04B1/16 ,  F22B37/248 ,  Y02E30/40

摘要： A nuclear reactor vessel structure includes an inner peripheral tube-shaped steel plate, an outer peripheral tube-shaped steel plate, and an intermediate tube-shaped steel plate disposed between the inner and outer peripheral tube-shaped steel plates, and is configured to support a nuclear reactor vessel on the inner peripheral side of a tube-shaped structure with concrete placed between the steel plates. The nuclear reactor vessel structure includes a support having a tube-shaped plate disposed on the inner peripheral side of the intermediate tube-shaped steel plate, and an annular plate which protrudes to the inner peripheral side of the tube-shaped plate and to which a connection section is affixed. The support is affixed to the concrete, which is placed between the inner peripheral and the intermediate tube-shaped steel plates, by first bar members, and the support is also affixed to the inner peripheral tube-shaped steel plate by second bar members.

摘要翻译： 核反应堆容器结构包括内周管状钢板，外周管状钢板和设置在内外管状钢板之间的中间管状钢板，构成为支承 在管状结构的内周侧具有放置在钢板之间的混凝土的核反应堆容器。 核反应堆容器结构包括具有设置在中间管状钢板的内周侧的管状板的支撑体和向管状板的内周侧突出的环状板， 连接部分被贴上。 支撑体通过第一杆构件固定在内周和中间管状钢板之间的混凝土上，并且支撑体也通过第二杆构件固定到内周管状钢板。

公开(公告)号：US20130127037A1

公开(公告)日：2013-05-23

申请号：US13638421

申请日：2011-03-03

申请人： Kentaro Mori ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Daisuke Ohshima ,  Yoshiki Nakashima ,  Hideya Murai

发明人： Kentaro Mori ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Daisuke Ohshima ,  Yoshiki Nakashima ,  Hideya Murai

IPC分类号： H01L23/34

CPC分类号： H01L23/34 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/04 ,  H01L24/12 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10342 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1435 ,  H01L2924/145 ,  H05K1/0203 ,  H05K1/185 ,  H05K2201/10515 ,  H01L2924/3512 ,  H01L2924/00

摘要： An object of the present invention is to provide a semiconductor device built-in substrate, which can be made thin and can suppress occurrence of warpage. The present invention provides a semiconductor substrate which is featured by including a first semiconductor device serving as a substrate, a second semiconductor device placed on the circuit surface side of the first semiconductor device in the state where the circuit surfaces of the first and second semiconductor devices are placed to face in the same direction, and an insulating layer incorporating therein the second semiconductor device, and which is featured in that a heat dissipation layer is formed at least between the first semiconductor device and the second semiconductor device, and in that the heat dissipation layer is formed on the first semiconductor device so as to extend up to the outside of the second semiconductor device.

摘要翻译： 本发明的一个目的是提供一种内置半导体器件的基板，它可以制成薄而可以抑制翘曲的发生。 本发明提供一种半导体衬底，其特征在于包括：第一半导体器件，用作衬底;第二半导体器件，其位于第一半导体器件的电路表面侧，处于第一和第二半导体器件的电路表面的状态 被放置成面向相同的方向，并且其中包含第二半导体器件的绝缘层，其特征在于至少在第一半导体器件和第二半导体器件之间形成散热层，并且其中的热量 散热层形成在第一半导体器件上，以便延伸到第二半导体器件的外部。

公开(公告)号：US20130026653A1

公开(公告)日：2013-01-31

申请号：US13636324

申请日：2011-03-22

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

IPC分类号： H01L21/56 ,  H01L23/48

CPC分类号： H05K1/185 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/18 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/4605 ,  H05K2201/09581 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2924/00

摘要： In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

摘要翻译： 在包含多个布线层和绝缘层的多层布线结构中包含半导体元件的半导体器件的制造方法中，将半导体元件安装在硅支撑体上，该硅支撑体的厚度减小到期望的厚度并且配备有 多个穿过厚度方向的通孔; 形成绝缘层以嵌入半导体元件; 那么在与硅半导体元件相连的硅支撑体的相对表面上形成多个布线层。 因此，可以减少在制造中在半导体元件附近发生的翘曲，从而改善整个半导体器件的翘曲轮廓。 此外，可以防止半导体元件变得无用，提高成品率，并且可以生产具有高密度封装性能的薄型半导体器件。