公开(公告)号：US08134231B2

公开(公告)日：2012-03-13

申请号：US12348543

申请日：2009-01-05

申请人： Hikari Sano ,  Yoshihiro Tomita ,  Takahiro Nakano

发明人： Hikari Sano ,  Yoshihiro Tomita ,  Takahiro Nakano

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L27/14618 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/014

摘要： A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made of a material having a thermal conductivity greater than that of the substrate formed in a non-penetrating hole having its opening on a reverse surface of the substrate.

摘要翻译： 一种半导体芯片，包括：包括前表面的基板; 形成在所述前表面上且包括多个半导体元件的集成电路; 以及形成在所述基板的与所述半导体元件中的至少一个相对应的区域中的散热塞。 散热塞由具有大于在其基板的背面上具有开口的非穿透孔中形成的基板的热导率的材料制成。

公开(公告)号：US20090059055A1

公开(公告)日：2009-03-05

申请号：US12195081

申请日：2008-08-20

申请人： Takahiro Nakano ,  Yoshihiro Tomita ,  Hikari Sano

发明人： Takahiro Nakano ,  Yoshihiro Tomita ,  Hikari Sano

IPC分类号： H04N5/225

CPC分类号： H04N5/2253 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14687 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11 ,  H01L2924/00014 ,  H04N5/2254 ,  H01L2224/05099

摘要： An optical device includes: an optical element including an imaging region, a peripheral circuit region formed at the rim of the imaging region and including a plurality of electrode portions, and a plurality of microlenses formed on the imaging region; a plurality of through-hole electrodes connected to the respective electrode portions and formed through the semiconductor substrate along the thickness of the semiconductor substrate; a plurality of metal interconnects connected to the respective through-hole electrodes and formed on a back surface of the semiconductor substrate opposite to a principal surface of the semiconductor substrate; an adhesive member formed on a surface of the optical element and made of a resin; and a transparent board bonded to the optical element with the adhesive member interposed therebetween. The transparent board has a planar shape larger than that of the optical element.

摘要翻译： 光学装置包括：光学元件，包括成像区域，形成在成像区域的边缘处并包括多个电极部分的外围电路区域和形成在成像区域上的多个微透镜; 多个通孔电极，其连接到各个电极部分并沿半导体衬底的厚度形成在半导体衬底上; 多个金属互连件，连接到相应的通孔电极并形成在与半导体衬底的主表面相对的半导体衬底的背面上; 形成在所述光学元件的表面上并由树脂制成的粘合部件; 以及粘合到光学元件上的透明板，其间插入有粘合构件。 透明板具有比光学元件大的平面形状。

公开(公告)号：US07960271B2

公开(公告)日：2011-06-14

申请号：US12203982

申请日：2008-09-04

申请人： Hideki Takehara ,  Yoshihiro Tomita ,  Seiji Fujiwara ,  Takahiro Nakano ,  Hikari Sano

发明人： Hideki Takehara ,  Yoshihiro Tomita ,  Seiji Fujiwara ,  Takahiro Nakano ,  Hikari Sano

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14104 ,  H01L2224/81143 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/207 ,  H01L2224/13099 ,  H01L2924/00012

摘要： The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps.

摘要翻译： 本发明提供一种能够抑制在回流加热期间由凸块的高度变化引起的不良连接的半导体器件，可以应用于窄的阵列间距，并且可以自由地调节凸块的高度。

公开(公告)号：US20090211793A1

公开(公告)日：2009-08-27

申请号：US12330923

申请日：2008-12-09

申请人： Takahiro NAKANO ,  Masanori Minamio ,  Yoshihiro Tomita ,  Hikari Sano

发明人： Takahiro NAKANO ,  Masanori Minamio ,  Yoshihiro Tomita ,  Hikari Sano

IPC分类号： H05K1/18 ,  H05K3/02

CPC分类号： H01L27/14636 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/351 ,  H05K1/115 ,  H05K3/388 ,  H05K2201/09509 ,  Y10T29/49155 ,  H01L2924/00

摘要： In a substrate module of the present invention, a connection electrode is provided on a first surface of a substrate, and a first penetrating hole portion is running through the substrate in a thickness direction thereof so as to reach a reverse surface of the connection electrode, with a penetrating electrode being provided inside the first penetrating hole portion. The penetrating electrode defines a depression in a position opposing the reverse surface of the connection electrode, and an upper portion of the penetrating electrode is thicker than a side portion of the penetrating electrode. The penetrating electrode is present also on a second surface of the substrate, and is connected to a wiring electrode on the second surface.

摘要翻译： 在本发明的基板模块中，在基板的第一面上设置有连接电极，第一贯通孔部在其厚度方向上贯穿基板，从而到达连接电极的背面， 其中穿透电极设置在第一穿透孔部分的内部。 穿透电极在与连接电极的反面相对的位置形成凹部，并且穿透电极的上部比穿透电极的侧部更厚。 穿透电极也存在于基板的第二表面上，并且连接到第二表面上的布线电极。

公开(公告)号：US20090065933A1

公开(公告)日：2009-03-12

申请号：US12203982

申请日：2008-09-04

申请人： Hideki Takehara ,  Yoshihiro Tomita ,  Seiji Fujiwara ,  Takahiro Nakano ,  Hikari Sano

发明人： Hideki Takehara ,  Yoshihiro Tomita ,  Seiji Fujiwara ,  Takahiro Nakano ,  Hikari Sano

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14104 ,  H01L2224/81143 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/207 ,  H01L2224/13099 ,  H01L2924/00012

摘要： The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps.

摘要翻译： 本发明提供一种能够抑制在回流加热期间由凸块的高度变化引起的不良连接的半导体器件，可以应用于窄的阵列间距，并且可以自由地调节凸块的高度。

公开(公告)号：US20110147905A1

公开(公告)日：2011-06-23

申请号：US13039937

申请日：2011-03-03

申请人： Masaki Utsumi ,  Hikari Sano ,  Hiroaki Fujimoto ,  Yoshihiro Tomita

发明人： Masaki Utsumi ,  Hikari Sano ,  Hiroaki Fujimoto ,  Yoshihiro Tomita

IPC分类号： H01L23/06 ,  H01L21/78

CPC分类号： H01L33/62 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14618 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions 4 are formed respectively on the top surfaces of the electrode portions. Moreover, an optical member pressed in contact with the protrusions is fixed on the semiconductor element with an adhesive.

摘要翻译： 在半导体元件中，形成上通孔导体部和下通孔导体部，使得上通孔导体部和下通孔导体部的接合面的孔径A小于孔径 B，半导体元件的主表面上的上通孔导体部分的孔径C和半导体元件另一表面上的下通孔导体部分的孔径C. 此外，电极部分分别形成在上通孔导体部分的顶表面上，突起4分别形成在电极部分的顶表面上。 此外，用粘合剂固定在半导体元件上与突起接触的光学部件。

公开(公告)号：US20100176475A1

公开(公告)日：2010-07-15

申请号：US12649524

申请日：2009-12-30

申请人： Hikari Sano ,  Yoshihiro Tomita

发明人： Hikari Sano ,  Yoshihiro Tomita

IPC分类号： H01L31/0232 ,  H01L31/0216 ,  H01L31/18

CPC分类号： H01L27/14625 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14685

摘要： An optical device according to an aspect of the present invention includes: a semiconductor substrate layer including a plurality of elements; at least one optical component which is formed at the first principal surface side of the semiconductor substrate layer and transmits incident light of desired wavelength; and an interconnect layer formed on second principal surface of the semiconductor substrate layer. In the semiconductor substrate layer, (i) a photoelectric conversion element region is formed at a position corresponding to the at least one optical component, and (ii) at least one element among the plurality of elements is formed near the second principal surface. At least a part of the at least one optical component is formed as a part of the semiconductor substrate layer, and the interconnect layer includes the conductive material electrically connected to the photoelectric conversion element region and the at least one element.

摘要翻译： 根据本发明的一个方面的光学器件包括：包括多个元件的半导体衬底层; 至少一个光学部件，形成在所述半导体衬底层的第一主表面侧并透射所需波长的入射光; 以及形成在所述半导体衬底层的第二主表面上的互连层。 在半导体衬底层中，（i）在与至少一个光学部件相对应的位置形成光电转换元件区域，（ii）在第二主表面附近形成多个元件中的至少一个元件。 所述至少一个光学部件的至少一部分形成为所述半导体衬底层的一部分，并且所述互连层包括与所述光电转换元件区域和所述至少一个元件电连接的所述导电材料。

公开(公告)号：US20100148294A1

公开(公告)日：2010-06-17

申请号：US12712420

申请日：2010-02-25

申请人： Kyoko FUJII ,  Takahiro Nakano ,  Hikari Sano

发明人： Kyoko FUJII ,  Takahiro Nakano ,  Hikari Sano

IPC分类号： H01L31/0216

CPC分类号： H04N5/2253 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627

摘要： An optical device such as an image sensor alleviates reduction in image quality caused by light reaching a peripheral circuit section other than a light receiving section. A semiconductor substrate includes an interconnect layer, a light receiving section provided with a plurality of light receiving elements on the interconnect layer, and a peripheral circuit section provided in a same layer as the light receiving section, and surrounding the light receiving section. Light entry elements are provided on a surface of the semiconductor substrate. A light shielding film is formed of a metal layer, and covers at least one part of a region corresponding to the peripheral circuit section. A first electrode is formed in the region corresponding to the peripheral circuit section, and in an opening of the light shielding film to be electrically isolated from the light shielding film.

摘要翻译： 诸如图像传感器的光学装置减轻了到达光接收部分以外的外围电路部分的光的图像质量的降低。 半导体衬底包括互连层，在互连层上设置有多个光接收元件的光接收部分和设置在与光接收部分相同的层中并围绕光接收部分的外围电路部分。 光入射元件设置在半导体衬底的表面上。 遮光膜由金属层形成，并且覆盖对应于外围电路部分的区域的至少一部分。 第一电极形成在与外围电路部分对应的区域中，并且在遮光膜的开口中与遮光膜电隔离。

公开(公告)号：US08810039B2

公开(公告)日：2014-08-19

申请号：US13323454

申请日：2011-12-12

申请人： Koji Takemura ,  Hiroshige Hirano ,  Masao Takahashi ,  Hikari Sano ,  Yutaka Itoh ,  Koji Koike

发明人： Koji Takemura ,  Hiroshige Hirano ,  Masao Takahashi ,  Hikari Sano ,  Yutaka Itoh ,  Koji Koike

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/66

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.

摘要翻译： 半导体器件包括：半导体衬底; 形成在半导体衬底上的第一层间绝缘膜; 形成在第一层间绝缘膜上方的焊盘; 以及在位于所述垫下方的所述第一层间绝缘膜的部分中彼此间隔开的多个第一互连。 在焊盘下面，第一互连以四边形的平面形状形成。

公开(公告)号：US20110095430A1

公开(公告)日：2011-04-28

申请号：US12984142

申请日：2011-01-04

申请人： Koji TAKEMURA ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

发明人： Koji TAKEMURA ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

IPC分类号： H01L23/485

CPC分类号： H01L23/585 ,  H01L21/76832 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

摘要翻译： 一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强 靠近密封圈。 芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层 使用通孔部分。