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    Semiconductor device
    1.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07035081B2

    公开(公告)日：2006-04-25

    申请号：US10478800

    申请日：2002-05-28

    申请人： Tatsuya Nagata ,  Seiji Miyamoto ,  Hideko Ando

    发明人： Tatsuya Nagata ,  Seiji Miyamoto ,  Hideko Ando

    IPC分类号： H01G4/228

    CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/10674

    摘要： The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise. A semiconductor device of the invention includes: a base (5) having front layers (9, 11) provided on respective sides of a core layer (7) formed by a printed circuit board, and a semiconductor chip (1) mounted on the base (5), wherein the semiconductor chip (1) is joined to one (9) of the front layers by using a joining member (3), and the other front layer (11) has a plurality of external terminals (55) arranged thereon, and the core layer (7) has a plurality of through-holes (41, 43, 45, 75, 77) formed therein to electrically connect the semiconductor chip (1) to the plurality of external terminals (55) together, and the plurality of through-holes (41, 43, 45, 75, 77) include a plurality of arrayed through-holes (41, 43, 45) arranged correspondingly to the arrangement of the plurality of external terminals (55) and one or more additional through-holes (75, 77) formed between the plurality of arrayed through-holes (41, 43, 45).

    摘要翻译： 本发明不需要增加半导体器件的尺寸并减少噪声的发生。 本发明的半导体器件包括：基底（5），其具有设置在由印刷电路板形成的芯层（7）的相应侧上的前层（9,11）和安装在基底上的半导体芯片（1） （5），其中所述半导体芯片（1）通过使用接合部件（3）接合到所述前层中的一个（9），并且所述另一个前层（11）具有布置在其上的多个外部端子（55） ，芯层（7）具有形成在其中的多个通孔（41,43,45,75,77），以将半导体芯片（1）与多个外部端子（55）电连接在一起，并且 多个通孔（41,43,45,75,77）包括与多个外部端子（55）的布置相对应布置的多个排列的通孔（41,43,45）和一个或多个附加的 形成在多个排列的通孔（41,43,45）之间的通孔（75,77）。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06747356B2

    公开(公告)日：2004-06-08

    申请号：US10386441

    申请日：2003-03-13

    申请人： Hideko Ando ,  Seiji Miyamoto

    发明人： Hideko Ando ,  Seiji Miyamoto

    IPC分类号： H01L2348

    CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/0298 ,  H05K3/4602 ,  H05K2201/0191

    摘要： Control of the characteristic impedance of wirings is performed with high accuracy. Relative to a first wiring of a second wiring layer arranged above a through hole of a core layer in a package board, the thickness of a first insulating layer between a first wiring layer on the surface of the core layer and the second wiring layer is made large, and the thickness of a second insulating layer between a third wiring layer that is a plane layer on the side of opposite thereto and the second wiring layer is made small, thereby allowing for: reducing the impedance coupling between the power plane of the first wiring layer on the surface of the core layer and the first and second wirings; reinforcing the impedance coupling between the power plane of the third wiring layer on the side opposite thereto and the first and second wirings; and achieving the reduction of the difference in the characteristic impedance between the first wiring arranged just above the through hole and the second wiring arranged away from just above the through hole.

    摘要翻译： 高精度地进行布线特性阻抗的控制。 相对于在封装基板中配置在芯层的通孔上方的第二布线层的第一布线，使得在芯层表面上的第一布线层和第二布线层之间的第一绝缘层的厚度 并且在与其相对侧的平面层的第三布线层和第二布线层之间的第二绝缘层的厚度变小，从而允许：降低第一布线层的第一布线层与第二布线层之间的阻抗耦合。 芯层表面上的布线层和第一和第二布线; 加强第三布线层的与其相反的一侧的电源面与第一和第二布线之间的阻抗耦合; 并且实现了布置在通孔正上方的第一布线与远离通孔正上方布置的第二布线之间的特性阻抗差的减小。

    Semiconductor device and a method of manufacturing the same
    7.
    发明授权
    Semiconductor device and a method of manufacturing the same 有权

    公开(公告)号：US06433412B1

    公开(公告)日：2002-08-13

    申请号：US09800589

    申请日：2001-03-08

    申请人： Hideko Ando ,  Hiroshi Kikuchi ,  Ikuo Yoshida ,  Toshihiko Sato ,  Tomo Shimizu

    发明人： Hideko Ando ,  Hiroshi Kikuchi ,  Ikuo Yoshida ,  Toshihiko Sato ,  Tomo Shimizu

    IPC分类号： H01L2302

    摘要： A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 using face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions and for relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.