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1.发明授权Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages 有权封装的半导体芯片，具有无冲击积层（BBUL）封装的无冲击模封装接口公开(公告)号：US09224674B2
公开(公告)日：2015-12-29
申请号：US13996495
申请日：2011-12-15
IPC分类号： H01L27/08 , H01L23/552 , H01L23/48 , H01L23/00
CPC分类号： H01L24/09 , H01L23/481 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L24/19 , H01L24/97 , H01L27/08 , H01L2224/04105 , H01L2224/08235 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15153 , H01L2924/00 , H01L2224/83 , H01L2224/82
摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.
摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。
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公开(公告)号：US20130277865A1
公开(公告)日：2013-10-24
申请号：US13977183
申请日：2011-10-31
申请人： Weng Hong Teh , John S. Guzek , Shan Zhong
发明人： Weng Hong Teh , John S. Guzek , Shan Zhong
IPC分类号： H01L23/498
CPC分类号： H01L25/0657 , H01L23/12 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/5389 , H01L25/105 , H01L2224/13147 , H01L2224/14181 , H01L2224/16225 , H01L2224/16227 , H01L2224/73 , H01L2225/06513 , H01L2225/06548 , H01L2225/06555 , H01L2225/06575 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.
摘要翻译： 描述了封装组件和封装集成电路芯片的方法。 公开的封装组件具有包括IC芯片的间隔件和凹陷区域。 提供了建立结构，使得能够例如三维（3D）封装（或封装（SiP）或多芯片模块系统）），片上3D封装和混合3D绑定。 本发明的实施例可以用于例如创建逻辑到存储器，存储器到存储器和逻辑到逻辑接口堆叠组件。
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3.发明授权公开(公告)号：US08937382B2
公开(公告)日：2015-01-20
申请号：US13169162
申请日：2011-06-27
申请人： Weng Hong Teh , John S. Guzek
发明人： Weng Hong Teh , John S. Guzek
IPC分类号： H01L23/495 , H01L23/31 , H01L21/56 , H01L23/00
CPC分类号： H05K3/32 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3121 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L2221/68372 , H01L2224/32245 , H01L2224/82001 , H01L2224/82002 , H01L2224/92244 , H01L2924/01006 , H01L2924/01029 , H01L2924/12042 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , Y10T29/49117 , Y10T29/4913 , H01L2924/00
摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.
摘要翻译： 本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。
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4.发明申请PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES 有权包装半导体套件，用于无阻堆叠接口（BBUL）包装公开(公告)号：US20130270715A1
公开(公告)日：2013-10-17
申请号：US13996495
申请日：2011-12-15
IPC分类号： H01L23/48
CPC分类号： H01L24/09 , H01L23/481 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L24/19 , H01L24/97 , H01L27/08 , H01L2224/04105 , H01L2224/08235 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15153 , H01L2924/00 , H01L2224/83 , H01L2224/82
摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.
摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。
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公开(公告)号：US09490196B2
公开(公告)日：2016-11-08
申请号：US13977183
申请日：2011-10-31
申请人： Weng Hong Teh , John S. Guzek , Shan Zhong
发明人： Weng Hong Teh , John S. Guzek , Shan Zhong
IPC分类号： H01L23/498 , H01L23/13 , H01L25/065 , H01L25/10 , H01L23/31
CPC分类号： H01L25/0657 , H01L23/12 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/5389 , H01L25/105 , H01L2224/13147 , H01L2224/14181 , H01L2224/16225 , H01L2224/16227 , H01L2224/73 , H01L2225/06513 , H01L2225/06548 , H01L2225/06555 , H01L2225/06575 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.
摘要翻译： 描述了封装组件和封装集成电路芯片的方法。 公开的封装组件具有包括IC芯片的间隔件和凹陷区域。 提供了建立结构，使得能够例如三维（3D）封装（或封装（SiP）或多芯片模块系统）），片上3D封装和混合3D绑定。 本发明的实施例可以用于例如创建逻辑到存储器，存储器到存储器和逻辑到逻辑接口堆叠组件。
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公开(公告)号：US20140091445A1
公开(公告)日：2014-04-03
申请号：US13631205
申请日：2012-09-28
IPC分类号： H01L23/34 , H01L21/98 , H01L23/495
CPC分类号： H01L24/20 , H01L21/56 , H01L23/34 , H01L23/36 , H01L23/367 , H01L23/3677 , H01L23/4334 , H01L23/49822 , H01L23/5389 , H01L24/19 , H01L25/18 , H01L2224/04105 , H01L2224/06181 , H01L2224/16145 , H01L2224/211 , H01L2224/32245 , H01L2224/73203 , H01L2224/73259 , H01L2224/73267 , H01L2924/10253 , H01L2924/15747 , H01L2924/00
摘要： An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
摘要翻译： 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。
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7.发明申请公开(公告)号：US20120326271A1
公开(公告)日：2012-12-27
申请号：US13169162
申请日：2011-06-27
申请人： Weng Hong Teh , John S. Guzek
发明人： Weng Hong Teh , John S. Guzek
IPC分类号： H01L29/66 , H01L21/56 , H01R43/00 , H01L21/283
CPC分类号： H05K3/32 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3121 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L2221/68372 , H01L2224/32245 , H01L2224/82001 , H01L2224/82002 , H01L2224/92244 , H01L2924/01006 , H01L2924/01029 , H01L2924/12042 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , Y10T29/49117 , Y10T29/4913 , H01L2924/00
摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.
摘要翻译： 本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。
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8.发明申请BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THIN DIELECTRIC LAYER 有权无刷建立层（BBUL）半导体封装超薄电介质层公开(公告)号：US20140264830A1
公开(公告)日：2014-09-18
申请号：US13801859
申请日：2013-03-13
IPC分类号： H01L23/498
CPC分类号： H01L23/49822 , H01L21/76807 , H01L21/7681 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L24/19 , H01L2221/1026 , H01L2224/12105 , H01L2924/18162
摘要： Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.
摘要翻译： 描述了具有超薄电介质层的无创积层（BBUL）半导体封装。 例如，一种装置包括具有多个外部导电凸块的集成电路的半导体管芯。 半导体封装容纳半导体管芯。 半导体封装包括设置在多个外部导电凸块上方的电介质层。 导电通孔设置在电介质层中并耦合到多个导电凸块之一。 导电线设置在电介质层上并耦合到导电通孔。
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9.发明申请公开(公告)号：US20140083858A1
公开(公告)日：2014-03-27
申请号：US13624288
申请日：2012-09-21
申请人： Weng Hong Teh , Kevin Lin , Feras Eid , Qing Ma
发明人： Weng Hong Teh , Kevin Lin , Feras Eid , Qing Ma
CPC分类号： H05K1/0272 , H01L21/568 , H01L24/19 , H01L24/20 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2924/1815 , H01L2924/18162 , H05K1/0212 , H05K1/185 , H05K3/0097 , H05K2201/097 , H05K2203/1536 , H05K2203/308 , Y10T29/4913
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将微流体管芯附接到封装结构，其中微流体管芯包括可以与设置在封装结构内的信号焊盘耦合的多个不对称电极。
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公开(公告)号：US20150217995A1
公开(公告)日：2015-08-06
申请号：US14129542
申请日：2013-09-27
发明人： Weng Hong Teh , Sarah K Haney , Chyi Hwang Lim
CPC分类号： B81C1/0015 , B81B3/0051 , B81B2207/015 , B81C1/00476 , B81C2203/0714 , B81C2203/0735 , B81C2203/0771 , H01L21/568 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/73267
摘要： A semiconductor package comprising a suspended beam portion including an arrangement of through-hole structures. In an embodiment, a first surface of the suspended beam portion includes edges each defining in part a respective through-hole of a plurality of through-holes extending between the first surface and a second surface. The first surface comprises a plurality of arm portions each located between a respective pair of edge-adjacent edges. The first surface comprises a plurality of node portions each located at a respective junction of three or more of the plurality of arm portions. In another embodiment, for each of the plurality of node portions, a respective total number of arm portions which join one another at the node portion is a number other than four, or two arm portions which join one another at the node portion have respective mid-lines which are oblique to one another.
摘要翻译： 一种半导体封装，包括包括通孔结构的布置的悬挂梁部分。 在一个实施例中，悬挂梁部分的第一表面包括边缘，每个边缘部分地限定在第一表面和第二表面之间延伸的多个通孔的相应通孔。 第一表面包括多个臂部分，每个臂部分位于相应的一对边缘相邻边缘之间。 第一表面包括多个节点部分，每个节点部分位于多个臂部分中的三个或更多个的相应接合处。 在另一个实施例中，对于多个节点部分中的每个节点部分，在节点部分处彼此连接的臂部分的相应总数是除四个之外的数量，或者在节点部分处彼此连接的两个臂部分分别具有中间 相互倾斜的线条
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