公开(公告)号：US09209124B2

公开(公告)日：2015-12-08

申请号：US13964999

申请日：2013-08-12

申请人： XINTEC INC.

发明人： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/58 ,  H01L23/525 ,  H01L29/06 ,  H01L21/683

CPC分类号： H01L23/585 ,  H01L21/283 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/1302 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。

公开(公告)号：US09030011B2

公开(公告)日：2015-05-12

申请号：US13959567

申请日：2013-08-05

申请人： Xintec Inc.

发明人： Chao-Yen Lin ,  Yi-Hang Lin

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/525 ,  H01L29/06

CPC分类号： H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

摘要： An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：载体基板; 具有上表面和下表面的半导体衬底，设置在载体衬底上; 位于所述半导体衬底的上表面上的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US09425134B2

公开(公告)日：2016-08-23

申请号：US14339323

申请日：2014-07-23

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  G06K9/00 ,  H01L25/065 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L23/49805 ,  G06K9/00006 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

摘要翻译： 提供芯片封装。 芯片封装包括具有上表面，下表面和侧壁的芯片。 芯片包括感测区域或器件区域以及与上表面相邻的信号焊盘区域。 浅凹陷结构位于信号垫区域的外侧，并且沿着侧壁从上表面向下表面延伸。 浅凹部结构在第一凹部下方具有至少第一凹部和第二凹部。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线的第一端位于浅凹陷结构中，并且电连接到再分配层。 电线的第二端用于外部电气连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US08963312B2

公开(公告)日：2015-02-24

申请号：US14339341

申请日：2014-07-23

申请人： Xintec Inc.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/49 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

摘要翻译： 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。

公开(公告)号：US08952501B2

公开(公告)日：2015-02-10

申请号：US13950101

申请日：2013-07-24

申请人： Xintec Inc.

发明人： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC分类号： H01L29/06 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683

CPC分类号： H01L23/49805 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有上表面和下表面的半导体衬底; 限定在所述半导体衬底中的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 至少两个从所述半导体衬底的上表面向下表面延伸的凹槽，其中所述凹槽的侧壁和底部一起形成所述半导体衬底的侧壁; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US09437478B2

公开(公告)日：2016-09-06

申请号：US14339360

申请日：2014-07-23

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen ,  Ho-Yin Yiu

IPC分类号： H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  G06K9/00 ,  H01L23/00 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L21/76802 ,  G06K9/00053 ,  H01L21/561 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

摘要翻译： 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09355975B2

公开(公告)日：2016-05-31

申请号：US14339355

申请日：2014-07-23

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen ,  Chi-Chang Liao

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L29/06 ,  H01L23/525 ,  H01L23/532 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L21/561 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10523 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3701 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

摘要翻译： 提供了包括具有上表面，下表面和侧壁的芯片的芯片封装。 芯片包括与上表面相邻的信号焊盘区域。 第一凹部沿着侧壁从上表面向下表面延伸。 至少一个第二凹部从第一凹部的第一底部向下表面延伸。 第一和第二凹部沿着上表面的侧面进一步横向延伸，并且沿着侧面延伸的第一凹部的长度大于沿着侧面延伸的第二凹部的长度。 再分配层电连接到信号焊盘区域并延伸到第二凹槽中。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09355970B2

公开(公告)日：2016-05-31

申请号：US14958155

申请日：2015-12-03

申请人： XINTEC INC.

发明人： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC分类号： H01L29/00 ,  H01L23/58 ,  H01L21/48 ,  H01L21/78 ,  H01L21/283

CPC分类号： H01L23/585 ,  H01L21/283 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/1302 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。

公开(公告)号：US09196594B2

公开(公告)日：2015-11-24

申请号：US14337121

申请日：2014-07-21

申请人： XINTEC INC.

发明人： Chao-Yen Lin ,  Yi-Hang Lin

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/525 ,  H01L29/06 ,  G06K9/00 ,  H05K1/18

CPC分类号： H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

摘要： An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.