公开(公告)号：US06856026B2

公开(公告)日：2005-02-15

申请号：US10616981

申请日：2003-07-11

申请人： Yuichiro Yamada ,  Tsuyoshi Hamatani

发明人： Yuichiro Yamada ,  Tsuyoshi Hamatani

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.The semiconductor chip has a semiconductor substrate 13, first external electrodes 21 formed on the first surface 14 of the semiconductor substrate 13, second external electrodes 22 formed on the second surface 17 of the semiconductor substrate 13 and through holes 16 created in the semiconductor substrate 13, wherein the through holes 16 are provided in the inclined planes 15 formed so that the inner angles made up of the second surface 17 and the inclined planes 15 are obtuse angles and the first external electrodes 21 and the second external electrodes 22 are electrically connected through conductive patterns 19 formed so as to follow the inner walls of the through holes 16 and the inclined planes 15.

摘要翻译： 即使在多个半导体芯片层叠在布线基板上的情况下，半导体芯片也不会增加半导体器件的厚度或电路板面积，其中半导体芯片被层叠，并且不增加半导体芯片之间的线长度 其工艺以及半导体器件等。半导体芯片具有半导体衬底13，形成在半导体衬底13的第一表面14上的第一外部电极21，形成在半导体衬底13上的第二外部电极22 半导体基板13的第二表面17和在半导体基板13中形成的通孔16，其中通孔16设置在倾斜平面15中，使得由第二表面17和倾斜平面15构成的内角是 钝角和第一外部电极21和第二外部电极22通过导电性电连接 erns 19形成为跟随通孔16和倾斜平面15的内壁。

公开(公告)号：US06693358B2

公开(公告)日：2004-02-17

申请号：US09972884

申请日：2001-10-10

申请人： Yuichiro Yamada ,  Tsuyoshi Hamatani

发明人： Yuichiro Yamada ,  Tsuyoshi Hamatani

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided. The semiconductor chip has a semiconductor substrate 13, first external electrodes 21 formed on the first surface 14 of the semiconductor substrate 13, second external electrodes 22 formed on the second surface 17 of the semiconductor substrate 13 and through holes 16 created in the semiconductor substrate 13, wherein the through holes 16 are provided in the inclined planes 15 formed so that the inner angles made up of the second surface 17 and the inclined planes 15 are obtuse angles and the first external electrodes 21 and the second external electrodes 22 are electrically connected through conductive patterns 19 formed so as to follow the inner walls of the through holes 16 and the inclined planes 15.

摘要翻译： 即使在多个半导体芯片层叠在布线基板上的情况下，半导体芯片也不会增加半导体器件的厚度或电路板面积，其中半导体芯片被层叠，并且不增加半导体芯片之间的线长度 其工艺以及半导体器件等。半导体芯片具有半导体衬底13，形成在半导体衬底13的第一表面14上的第一外部电极21，形成在半导体衬底13上的第二外部电极22 半导体基板13的第二表面17和在半导体基板13中形成的通孔16，其中通孔16设置在倾斜平面15中，使得由第二表面17和倾斜平面15构成的内角是 钝角和第一外部电极21和第二外部电极22通过导电性电连接 erns 19形成为跟随通孔16和倾斜平面15的内壁。

公开(公告)号：US20050133892A1

公开(公告)日：2005-06-23

申请号：US11042163

申请日：2005-01-26

申请人： Hiroaki Fujimoto ,  Tsuyoshi Hamatani ,  Toru Nomura

发明人： Hiroaki Fujimoto ,  Tsuyoshi Hamatani ,  Toru Nomura

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/50 ,  H01L25/10 ,  H01L23/52

CPC分类号： H01L23/49548 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.

摘要翻译： 公开了一种半导体器件，其包括具有多个电极的半导体元件，设置在半导体元件周围的多个外部电极，电连接在多个外部电极中的至少一个表面之间的细线， 半导体元件的多个电极中的至少一个以及密封半导体元件，多个外部电极和细线的外形为长方体的封装树脂，其中半导体元件的底面和底部 多个外部电极的表面从封装树脂的底面露出，半导体元件的上表面和多个外部电极的上表面大致共面。

公开(公告)号：US20050054188A1

公开(公告)日：2005-03-10

申请号：US10933423

申请日：2004-09-03

申请人： Masazumi Matsuura ,  Hiroshi Horibe ,  Susumu Matsumoto ,  Tsuyoshi Hamatani

发明人： Masazumi Matsuura ,  Hiroshi Horibe ,  Susumu Matsumoto ,  Tsuyoshi Hamatani

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/04941 ,  H01L2224/45099

摘要： A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.

摘要翻译： 半导体器件包括：分别形成在半导体衬底上并具有不同弹性模量的多种层间绝缘膜; 布置在所述多种层间绝缘膜上的金属焊盘; 具有最低弹性模量的低弹性模量并且具有位于金属垫下方的开口的层间绝缘膜，具有大于层间绝缘膜的弹性模量的弹性模量的非低弹性模量的层间绝缘膜为 所述低弹性模量与所述低弹性模量的所述层间绝缘膜层叠，并且在所述开口和围绕所述开口的区域上连续延伸，以及布置在所述金属焊盘下方的金属互连层，填充所述层间绝缘体 低弹性模量的薄膜，并且与非低弹性模量的层间绝缘膜接触。

公开(公告)号：US20070029641A1

公开(公告)日：2007-02-08

申请号：US11498188

申请日：2006-08-03

申请人： Tsuyoshi Hamatani ,  Yukitoshi Ota

发明人： Tsuyoshi Hamatani ,  Yukitoshi Ota

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.

摘要翻译： 沿着半导体元件区域和划线格栅区域之间的边界连续地形成密封环，辅助部件沿着密封环间歇地布置，密封环由金属层构成。

公开(公告)号：US20070023927A1

公开(公告)日：2007-02-01

申请号：US11487329

申请日：2006-07-17

申请人： Noriyuki Nagai ,  Tsuyoshi Hamatani ,  Tadaaki Mimura

发明人： Noriyuki Nagai ,  Tsuyoshi Hamatani ,  Tadaaki Mimura

IPC分类号： H01L23/48

CPC分类号： H01L23/5225 ,  H01L23/525 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01033

摘要： When an interlayer film (22) is formed to have a large thickness and an electrode pad (11) is partly or wholly led out from an active region (16), an I/O region (15) can be reduced in area. Thus, it is possible to reduce an area of a semiconductor device.

摘要翻译： 当层间膜（22）形成为具有大的厚度并且电极焊盘（11）部分或全部从有源区域（16）引出时，I / O区域（15）的面积可以减小。 因此，可以减小半导体器件的面积。

公开(公告)号：US07125751B2

公开(公告)日：2006-10-24

申请号：US11042163

申请日：2005-01-26

申请人： Hiroaki Fujimoto ,  Tsuyoshi Hamatani ,  Toru Nomura

发明人： Hiroaki Fujimoto ,  Tsuyoshi Hamatani ,  Toru Nomura

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L23/49548 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.

摘要翻译： 公开了一种半导体器件，其包括具有多个电极的半导体元件，设置在半导体元件周围的多个外部电极，电连接在多个外部电极中的至少一个表面之间的细线， 半导体元件的多个电极中的至少一个以及密封半导体元件，多个外部电极和细线的外形为长方体的封装树脂，其中半导体元件的底面和底部 多个外部电极的表面从封装树脂的底面露出，半导体元件的上表面和多个外部电极的上表面大致共面。

公开(公告)号：US07777304B2

公开(公告)日：2010-08-17

申请号：US11498188

申请日：2006-08-03

申请人： Tsuyoshi Hamatani ,  Yukitoshi Ota

发明人： Tsuyoshi Hamatani ,  Yukitoshi Ota

IPC分类号： H01L23/544

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.

摘要翻译： 沿着半导体元件区域和划线格栅区域之间的边界连续地形成密封环，辅助部件沿着密封环间歇地布置，密封环由金属层构成。

公开(公告)号：US20050173801A1

公开(公告)日：2005-08-11

申请号：US11046697

申请日：2005-02-01

申请人： Tadaaki Mimura ,  Tsuyoshi Hamatani ,  Atuhito Mizutani ,  Kenji Ueda

发明人： Tadaaki Mimura ,  Tsuyoshi Hamatani ,  Atuhito Mizutani ,  Kenji Ueda

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19043

摘要： A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal (61) formed in the top layer, a second pad metal (62) formed under the first pad metal (61) via an interlayer insulating film (71), and vias (63) which penetrate the interlayer insulating film (71) and electrically connect the first pad metal (61) and the second pad metal (62). The first pad metal (61) and the second pad metal (62) have edges displaced from each other so as not to be aligned with each other along the thickness direction of each layer. Thus, it is possible to reduce stress occurring on an edge of the second pad metal (62), thereby reducing damage on the interlayer insulating film (71) and so on.

摘要翻译： 用作半导体器件的外部连接用电极的焊盘部分包括形成在顶层中的第一焊盘金属（61），经由层间绝缘膜形成在第一焊盘金属（61）下面的第二焊盘金属（62） 71）和穿过层间绝缘膜（71）并使第一焊盘金属（61）和第二焊盘金属（62）电连接的通孔（63）。 第一焊盘金属（61）和第二焊盘金属（62）具有沿着各层的厚度方向彼此不相对的边缘。 因此，可以减少在第二焊盘金属（62）的边缘产生的应力，从而减少对层间绝缘膜（71）的损伤等。

公开(公告)号：US06603194B2

公开(公告)日：2003-08-05

申请号：US09879082

申请日：2001-06-13

申请人： Masaki Utsumi ,  Masashi Funakoshi ,  Tsuyoshi Hamatani ,  Takeshi Morikawa ,  Yukio Nakabayashi

发明人： Masaki Utsumi ,  Masashi Funakoshi ,  Tsuyoshi Hamatani ,  Takeshi Morikawa ,  Yukio Nakabayashi

IPC分类号： H01L23495

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.