Rotatable and tunable heaters for semiconductor furnace
    6.
    发明授权
    Rotatable and tunable heaters for semiconductor furnace 有权
    适用于半导体炉的可旋转和可调加热器

    公开(公告)号:US08536491B2

    公开(公告)日:2013-09-17

    申请号:US12409880

    申请日:2009-03-24

    IPC分类号: F27D11/00 H01L21/31 H01L21/44

    摘要: A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of rotatable heaters arranged and operative to heat the chamber. In one embodiment, spacing between the sidewall heaters is adjustable. The heating system controls temperature variations within the chamber and promotes uniform film deposit thickness on the wafers.

    摘要翻译: 适用于晶圆化学气相沉积处理的半导体炉。 该炉包括具有顶部,底部,侧壁和用于可拆卸地保持一批垂直堆叠的晶片的内部空腔的热反应室。 提供了一种加热系统,其包括多个可旋转的加热器,其布置并可操作以加热该腔室。 在一个实施例中,侧壁加热器之间的间隔是可调节的。 加热系统控制室内的温度变化并且促进在晶片上均匀的膜沉积物厚度。

    METHOD AND SYSTEM FOR LOW TEMPERATURE ION IMPLANTATION
    8.
    发明申请
    METHOD AND SYSTEM FOR LOW TEMPERATURE ION IMPLANTATION 审中-公开
    用于低温离子植入的方法和系统

    公开(公告)号:US20100181500A1

    公开(公告)日:2010-07-22

    申请号:US12355443

    申请日:2009-01-16

    IPC分类号: H01J37/08

    CPC分类号: C30B31/22

    摘要: A method comprises pre-cooling a first semiconductor wafer outside of a process chamber, from a temperature at or above 15° C. to a temperature below 5° C. The pre-cooled first wafer is placed inside the process chamber after performing the pre-cooling step. A low-temperature ion implantation is performed on the first wafer after placing the first wafer.

    摘要翻译: 一种方法包括将处理室外的第一半导体晶片从等于或高于15℃的温度预先冷却至低于5℃的温度。预冷却的第一晶片在执行预处理之后放置在处理室内部 冷却步骤 在放置第一晶片之后,在第一晶片上进行低温离子注入。

    Optimizing light extraction efficiency for an LED wafer
    9.
    发明授权
    Optimizing light extraction efficiency for an LED wafer 有权
    优化LED晶圆的光提取效率

    公开(公告)号:US09324624B2

    公开(公告)日:2016-04-26

    申请号:US13431165

    申请日:2012-03-27

    摘要: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.

    摘要翻译: 本发明涉及一种制造发光二极管(LED)晶片的方法。 该方法首先确定LED晶片的目标表面形态。 目标表面形态为LED晶圆上的LED产生最大的光输出。 蚀刻LED晶片以形成粗糙的晶片表面。 此后,使用激光扫描显微镜,该方法研究了LED晶片的实际表面形态。 此后,如果实际的表面形态与目标表面形态不同,超过可接受的极限,则该方法重复一次或多次蚀刻步骤。 通过调整一个或多个蚀刻参数重复蚀刻。

    Opto-electronic device
    10.
    发明授权
    Opto-electronic device 有权
    光电器件

    公开(公告)号:US08729525B2

    公开(公告)日:2014-05-20

    申请号:US12547073

    申请日:2009-08-25

    IPC分类号: H01L29/06 H01L33/06

    CPC分类号: H01L33/06 H01L33/325

    摘要: The present application relates to an opto-electronic device. The opto-electronic device includes an n-cladding layer, a p-cladding layer and a multi-quantum well structure. The multi-quantum well structure is located between the p-cladding layer and the n-cladding layer, and includes a plurality of barrier layers, a plurality of well layers and a barrier tuning layer. The barrier tuning layer is made by doping the barrier layer adjacent to the p-cladding layer with an impurity therein for changing an energy barrier thereof to improve the light extraction efficiency of the opto-electronic device.

    摘要翻译: 本申请涉及一种光电器件。 光电器件包括n包层,p包层和多量子阱结构。 多量子阱结构位于p包覆层和n包层之间,并且包括多个势垒层,多个阱层和势垒调整层。 阻挡层调整层是通过将与p型包层相邻的势垒层与其中的杂质掺杂以改变其能量势垒而制成的,以提高光电器件的光提取效率。