公开(公告)号：US08349628B2

公开(公告)日：2013-01-08

申请号：US13053701

申请日：2011-03-22

申请人： Yung-Chang Chen ,  Hsin-Hsien Wu ,  Chyi Shyuan Chern ,  Ching-Wen Hsiao ,  Fu-Wen Liu ,  Kuang-Huan Hsu

发明人： Yung-Chang Chen ,  Hsin-Hsien Wu ,  Chyi Shyuan Chern ,  Ching-Wen Hsiao ,  Fu-Wen Liu ,  Kuang-Huan Hsu

IPC分类号： H01L21/00

CPC分类号： H01L33/505 ,  H01L25/167 ,  H01L33/486 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

摘要： An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.

摘要翻译： 本公开的实施例包括制造多个发光二极管器件的方法。 提供多个LED管芯。 LED管芯结合到载体衬底。 包含多个开口的图案化掩模层形成在载体衬底上。 多个LED管芯中的每一个分别通过多个开口中的一个露出。 多个开口中的每一个都填充有荧光体。 磷光体被固化。 对磷光体和图案化掩模层进行抛光以使覆盖多个LED管芯中的每一个的磷光体变薄。 在抛光荧光体之后去除图案化的掩模层。

公开(公告)号：US08906712B2

公开(公告)日：2014-12-09

申请号：US13112046

申请日：2011-05-20

申请人： Hsin-Hsien Wu ,  Chyi Shyuan Chern ,  Chun-Lin Chang ,  Ching-Wen Hsiao ,  Kuang-Huan Hsu

发明人： Hsin-Hsien Wu ,  Chyi Shyuan Chern ,  Chun-Lin Chang ,  Ching-Wen Hsiao ,  Kuang-Huan Hsu

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L33/22 ,  H01L33/32

CPC分类号： H01L33/22 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/26593 ,  H01L33/0025 ,  H01L33/06 ,  H01L33/32

摘要： A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process.

摘要翻译： 一种方法包括提供包括衬底和设置在衬底上的氮化镓（GaN）层）的LED元件。 处理GaN层。 该处理包括在GaN层上执行离子注入工艺。 离子注入工艺可以提供GaN层的粗糙化表面区域。 在一个实施例中，离子注入过程在小于约25摄氏度的温度下进行。 在另一个实施例中，在离子注入过程期间，衬底处于低于约零摄氏度的温度。

公开(公告)号：US20120292629A1

公开(公告)日：2012-11-22

申请号：US13112046

申请日：2011-05-20

申请人： Hsin-Hsien Wu ,  Chyi Shyuan Chern ,  Chun-Lin Chang ,  Ching-Wen Hsiao ,  Kuang-Huan Hsu

发明人： Hsin-Hsien Wu ,  Chyi Shyuan Chern ,  Chun-Lin Chang ,  Ching-Wen Hsiao ,  Kuang-Huan Hsu

IPC分类号： H01L33/60

CPC分类号： H01L33/22 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/26593 ,  H01L33/0025 ,  H01L33/06 ,  H01L33/32

摘要： A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process.

摘要翻译： 一种方法包括提供包括衬底和设置在衬底上的氮化镓（GaN）层）的LED元件。 处理GaN层。 该处理包括在GaN层上执行离子注入工艺。 离子注入工艺可以提供GaN层的粗糙化表面区域。 在一个实施例中，离子注入过程在小于约25摄氏度的温度下进行。 在另一个实施例中，在离子注入过程期间，衬底处于低于约零摄氏度的温度。

公开(公告)号：US09679836B2

公开(公告)日：2017-06-13

申请号：US13298102

申请日：2011-11-16

申请人： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00

摘要： A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US09613917B2

公开(公告)日：2017-04-04

申请号：US13435809

申请日：2012-03-30

申请人： Ching-Wen Hsiao ,  Chen-Shien Chen

发明人： Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L21/50 ,  H01L23/64 ,  H01L23/538 ,  H01L23/14 ,  H01L21/48 ,  H01L25/10 ,  H01L49/02 ,  H01L23/498

CPC分类号： H01L25/105 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/647 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L28/20 ,  H01L28/60 ,  H01L28/90 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

摘要： A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.

公开(公告)号：US09449941B2

公开(公告)日：2016-09-20

申请号：US13178161

申请日：2011-07-07

申请人： Pei-Chun Tsai ,  Sheng-Yu Wu ,  Ching-Wen Hsiao ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Chung-Shi Liu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Pei-Chun Tsai ,  Sheng-Yu Wu ,  Ching-Wen Hsiao ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Chung-Shi Liu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L29/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/48

摘要： A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections.

摘要翻译： 封装封装（PoP）包括具有多个衬底迹线的衬底，通过多个贴合在轨迹连接与衬底连接的衬底顶部的第一功能芯片，以及顶部上的第二功能芯片 的第一功能芯片，直接连接到基板。 另一个封装封装（PoP）包括：具有多个衬底迹线的衬底，通过在连接的SMD焊盘上形成的多个焊接掩模限定（SMD）连接到衬底的顶部上的第一功能芯片 焊料凸点，以及位于第一功能芯片顶部的第二功能芯片，通过多个贴合在线跟踪连接直接连接到基板。

公开(公告)号：US09219106B2

公开(公告)日：2015-12-22

申请号：US13198783

申请日：2011-08-05

申请人： Yen-Liang Lin ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Tsung-Ding Wang

发明人： Yen-Liang Lin ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Tsung-Ding Wang

IPC分类号： H01L27/08 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0103 ,  H01L2924/01083

摘要： A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

摘要翻译： 提供了一种用于提供具有高质量因子（Q）的集成电感器的系统和方法。 一个实施例包括位于导电螺旋中心的磁芯。 磁芯增加了集成电感器的电感，使得电感器可用于诸如RF扼流圈的应用中。 磁芯可以以与下凸缘金属化相同的方式和时间形成。

公开(公告)号：US08736050B2

公开(公告)日：2014-05-27

申请号：US12831819

申请日：2010-07-07

申请人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

发明人： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/13 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/818 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552

摘要： An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

摘要翻译： 集成电路结构包括半导体衬底; 穿过半导体衬底的导电通孔（TSV）; 以及覆盖半导体衬底并电连接到导电通孔的含铜柱。

公开(公告)号：US20130270682A1

公开(公告)日：2013-10-17

申请号：US13444674

申请日：2012-04-11

申请人： Yen-Chang Hu ,  Ching-Wen Hsiao ,  Chih-Hua Chen ,  Chen-Shien Chen ,  Tin-Hao Kuo

发明人： Yen-Chang Hu ,  Ching-Wen Hsiao ,  Chih-Hua Chen ,  Chen-Shien Chen ,  Tin-Hao Kuo

IPC分类号： H01L25/065 ,  H01L21/98

CPC分类号： H01L25/50 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/81805

摘要： Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.

公开(公告)号：US20130256836A1

公开(公告)日：2013-10-03

申请号：US13435809

申请日：2012-03-30

申请人： Ching-Wen Hsiao ,  Chen-Shien Chen

发明人： Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L27/10 ,  H01L27/08 ,  H01L21/02

CPC分类号： H01L25/105 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/647 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L28/20 ,  H01L28/60 ,  H01L28/90 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

摘要： A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.

摘要翻译： 用于封装封装（PoP）器件的软件包。 封装包括基板，形成在基板上的聚合物层，形成在聚合物层中的第一通孔，以及设置在第一通孔中以形成第一无源器件的材料。 材料可以是高介电常数介电材料，以便形成电容器或电阻材料以形成电阻器。