专利检索 ap:("Zvi Or-Bach" OR "Brian Cronquist" OR "Israel Beinglass" OR "Jan Lodewijk de Jong" OR "Deepak C. Sekar" OR "Paul Lim") AND inv:"Deepak C. Sekar" 第 1 页

1.

发明授权
Semiconductor device and structure 有权
标题翻译：半导体器件及结构

公开(公告)号：US08362482B2

公开(公告)日：2013-01-29

申请号：US13016313

申请日：2011-01-28

申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Paul Lim

发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Paul Lim

IPC分类号： H01L21/00 , H01L29/10 , H01L33/00 , H01L21/70

CPC分类号： H01L21/8221 , H01L21/6835 , H01L21/76254 , H01L21/823828 , H01L21/84 , H01L23/3677 , H01L23/481 , H01L23/5252 , H01L24/05 , H01L24/13 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/10802 , H01L27/10873 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/112 , H01L27/11206 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L27/1214 , H01L27/1266 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7881 , H01L29/792 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/0401 , H01L2224/16145 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01051 , H01L2924/01066 , H01L2924/01068 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15788 , H01L2924/1579 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00015 , H01L2924/01031 , H01L2924/3512 , H01L2924/00 , H01L2224/80001 , H01L2224/05599 , H01L2924/00012

摘要： A semiconductor device including a first layer including first transistors, wherein first logic circuits are constructed by the first transistors, and wherein the first logic circuits include at least one of Inverter, NAND gate, or NOR gate; and a second layer overlaying said first layer, the second layer including second transistors, wherein second logic circuits are constructed by the second transistors; wherein each logic circuit in the first logic circuits has inputs and at least one first output, the inputs are connected to the second logic circuits; wherein each logic circuit in the second logic circuits has a second output, and wherein the first transistors include first selectors adapted to selectively replace at least one of the at least one first outputs with at least one of the second outputs.

摘要翻译： 一种半导体器件，包括包括第一晶体管的第一层，其中第一逻辑电路由第一晶体管构成，并且其中第一逻辑电路包括反相器，非门或或非门中的至少一个; 以及覆盖所述第一层的第二层，所述第二层包括第二晶体管，其中第二逻辑电路由第二晶体管构成; 其中所述第一逻辑电路中的每个逻辑电路具有输入和至少一个第一输出，所述输入连接到所述第二逻辑电路; 其中所述第二逻辑电路中的每个逻辑电路具有第二输出，并且其中所述第一晶体管包括适于使用所述第二输出中的至少一个选择性地替换所述至少一个第一输出中的至少一个的第一选择器。

2.

发明授权
Method for fabrication of configurable systems 有权
标题翻译：可配置系统的制造方法

公开(公告)号：US08664042B2

公开(公告)日：2014-03-04

申请号：US13471009

申请日：2012-05-14

申请人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong

发明人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong

IPC分类号： H01L21/00

CPC分类号： H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/36 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L27/0688 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01066 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H03K19/177 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

摘要： A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

摘要翻译： 一种构建可配置系统的方法，所述方法包括：提供包括第一管芯和第二管芯的第一可配置系统，其中第一管芯和第二管芯之间的连接包括穿硅通孔（“TSV”），其中使用第一骰子线从第一晶片切下第一芯片; 提供包括第三管芯和第四管芯的第二可配置系统，其中第三管芯和第四管芯之间的连接包括穿硅通孔（“TSV”），其中使用第三管芯从第三晶片切割第三管芯线条以及使用相同的至少20个掩模来处理所述第一晶片和所述第三晶片; 其中第一骰子线与第三骰子线基本上不同，并且其中第二骰子包括用于将第一可配置系统连接到外部装置的可配置I / O。

3.

发明授权
Semiconductor device and structure 有权
标题翻译：半导体器件及结构

公开(公告)号：US08395191B2

公开(公告)日：2013-03-12

申请号：US12900379

申请日：2010-10-07

申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Zeev Wurman

发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Zeev Wurman

IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76 , H01L29/76 , H01L29/772 , H01L25/065

CPC分类号： H01L27/0688 , G03F9/7076 , G03F9/7084 , H01L21/268 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823871 , H01L21/84 , H01L23/367 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/544 , H01L24/73 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11551 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/42392 , H01L29/458 , H01L29/66272 , H01L29/66545 , H01L29/66621 , H01L29/66848 , H01L29/66901 , H01L29/732 , H01L29/78639 , H01L29/78642 , H01L29/78645 , H01L29/808 , H01L29/812 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/80001 , H01L2924/00012 , H01L2924/01015

摘要： A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.

摘要翻译： 一种半导体器件，包括具有第一晶体管的第一单晶层和第一对准标记; 覆盖所述第一单晶层的至少一个金属层，其中所述至少一个金属层包括铜或铝; 以及包括激活的掺杂剂区域的第二层，所述第二层覆盖所述至少一个金属层，其中所述第二层包括第二晶体管，其中所述第二晶体管被处理成与所述第一对准标记对齐，具有小于100nm的对准误差，第二晶体管包括单晶，水平取向晶体管。

4.

发明授权
Method for fabrication of a semiconductor device and structure 有权
标题翻译：半导体器件和结构的制造方法

公开(公告)号：US07960242B2

公开(公告)日：2011-06-14

申请号：US12847911

申请日：2010-07-30

申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar

发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar

IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76

CPC分类号： G11C17/14 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/36 , H01L23/481 , H01L23/5252 , H01L23/544 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0207 , H01L27/0688 , H01L27/0694 , H01L27/092 , H01L27/105 , H01L27/10873 , H01L27/10876 , H01L27/10897 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11803 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01066 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H03K17/687 , H03K19/0948 , H03K19/17704 , H03K19/17756 , H03K19/17764 , H03K19/17796 , H01L2924/00 , H01L2224/80001 , H01L2224/05599 , H01L2924/00012

摘要： A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

摘要翻译： 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用基于所述第一对准标记和所述第二对准标记之间的未对准的对准来执行光刻。

5.

发明授权
System comprising a semiconductor device and structure 有权
标题翻译：包括半导体器件和结构的系统

公开(公告)号：US08907442B2

公开(公告)日：2014-12-09

申请号：US13492382

申请日：2012-06-08

申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Zeev Wurman

发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Zeev Wurman

IPC分类号： H01L21/50 , H01L21/98 , H01L21/822 , G03F9/00 , H01L21/762 , H01L21/84 , H01L23/544 , H01L27/02 , H01L27/06 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/112 , H01L27/115 , H01L27/118 , H01L27/12 , H01L23/48

CPC分类号： H01L27/0688 , G03F9/7076 , G03F9/7084 , H01L21/268 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823871 , H01L21/84 , H01L23/367 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/544 , H01L24/73 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11551 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/42392 , H01L29/458 , H01L29/66272 , H01L29/66545 , H01L29/66621 , H01L29/66848 , H01L29/66901 , H01L29/732 , H01L29/78639 , H01L29/78642 , H01L29/78645 , H01L29/808 , H01L29/812 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/80001 , H01L2924/00012 , H01L2924/01015

摘要： A semiconductor device, including: a first layer including first transistors; an interconnection layer overlying the first transistors, the interconnection layer providing interconnection for the first transistors; a bonding layer overlying the interconnection layer; a second layer overlying the bonding layer; and a carrier substrate for the transferring of the second layer, where the second layer includes at least one through second layer via, where the at least one through second layer via has a diameter of less than 100 nm, where the second layer includes a plurality of second transistors, and where the second layer is transferred from a donor wafer.

摘要翻译： 一种半导体器件，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管的互连层，所述互连层为所述第一晶体管提供互连; 覆盖所述互连层的接合层; 覆盖结合层的第二层; 以及用于转移第二层的载体衬底，其中第二层包括至少一个贯穿第二层通孔，其中至少一个贯穿第二层通孔具有小于100nm的直径，其中第二层包括多个的第二晶体管，并且其中第二层从施主晶片转移。

6.

发明授权
Method for fabrication of a semiconductor device and structure 有权
标题翻译：半导体器件和结构的制造方法

公开(公告)号：US08378494B2

公开(公告)日：2013-02-19

申请号：US13162154

申请日：2011-06-16

申请人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong

发明人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong

IPC分类号： H01L23/58 , H01L23/528 , H01L21/98

CPC分类号： H01L27/08 , H01L21/26506 , H01L21/26513 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L23/544 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/00011 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/80001

摘要： A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

摘要翻译： 一种半导体器件，包括：第一单晶硅层，包括第一晶体管，第一对准标记和覆盖所述第一单晶硅层的至少一个金属层，其中所述至少一个金属层比其它材料包含铜或铝; 覆盖所述至少一个金属层的第二层，所述第二层包括第二晶体管，第二对准标记和穿过所述第二层的通孔，其中所述通孔是所述第一晶体管和所述第二晶体管之间的连接路径的一部分，其中所述通孔的对准基于所述第一对准标记和所述第二对准标记，并且受到所述第一对准标记和所述第二对准标记之间的距离的影响。