公开(公告)号：US5323520A

公开(公告)日：1994-06-28

申请号：US054910

申请日：1993-04-29

申请人： Michael G. Peters ,  William T. Chou ,  Wen-chou V. Wang ,  Michael G. Lee ,  Solomon I. Beilin

发明人： Michael G. Peters ,  William T. Chou ,  Wen-chou V. Wang ,  Michael G. Lee ,  Solomon I. Beilin

IPC分类号： H01L27/04 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01L21/822 ,  H05K1/11 ,  H05K1/16

CPC分类号： H01G4/232 ,  H01G4/306 ,  H05K1/162 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/1305 ,  H05K1/112 ,  H05K2201/0317 ,  H05K2201/09309 ,  H05K2203/0315 ,  Y10T29/435 ,  Y10T29/49165

摘要： A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.

摘要翻译： 通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。 将背面金属化层序列施加到基底基板的背面。 底部接触层序列被施加到基底基板的前侧表面。 形成底部接触电源端子，并且将底部接触金属化层施加到底部接触层的表面。 去除金属化层的一部分，并在底部接触金属化层的表面上形成绝缘层。 在绝缘层的表面形成接地金属化馈通和功率金属化馈通。 顶层接触层序列被施加到绝缘层的表面，形成前侧接地端子和前端电源端子。 背面接地端子和背面电源端子形成在基底基板的背面。

公开(公告)号：US06662443B2

公开(公告)日：2003-12-16

申请号：US09935378

申请日：2001-08-22

申请人： William T. Chou ,  Solomon Beilin ,  Michael G. Lee ,  Michael G. Peters ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon Beilin ,  Michael G. Lee ,  Michael G. Peters ,  Wen-chou Vincent Wang

IPC分类号： H01K310

CPC分类号： H05K3/423 ,  H05K3/0035 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of fabricating a multilayer interconnected substrate is disclosed. In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface. A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate. A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate. The blind via site is filled with a conductive material by an electrolytic plating process.

摘要翻译： 公开了一种制造多层互连衬底的方法。 在一个实施例中，该方法包括提供具有电介质基底的结构，其具有第一基本上平坦的表面和相对的第二基本上平坦的表面。 第一导电层设置在电介质基板的第一基本上平坦的表面上，并且在第一导电层和电介质基板之间存在界面。 在该结构中形成盲通孔部位，并且通过电介质基板到第一导电层和电介质基板之间的界面。 盲孔通过电镀工艺填充导电材料。

公开(公告)号：US06197664B1

公开(公告)日：2001-03-06

申请号：US09229503

申请日：1999-01-12

申请人： Michael G. Lee ,  Michael G. Peters ,  William T. Chou

发明人： Michael G. Lee ,  Michael G. Peters ,  William T. Chou

IPC分类号： H01L21326

CPC分类号： H05K3/423 ,  C25D7/123 ,  H05K3/427 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  H05K2203/105

摘要： A method for plating conductive material in through apertures and blind apertures of a substrate which has a conductive material on its upper and lower surfaces. In a typical configuration for plating a via, there is a first region of conductive material adjacent to, but outside of, the aperture which forms the via and a second region of conductive material inside of the aperture. The second conductive region is selected to be the cathode of the plating process. The structure is placed in a plating bath, a first potential is applied to the first region of conductive material, and a second potential is applied to the second region of conductive material, with the second potential being different from the first potential. Under these conditions, material will plate onto the second region of conductive material to fill the aperture. The value of the first potential is preferably selected to substantially reduce the rate at which the first region of conductive material is etched by the plating bath, and may be used to cause material to be plated onto first region, but at a slower rate than the plating of the second conductive region.

摘要翻译： 一种用于在导电材料的上部和下部表面上具有导电材料的通孔和盲孔中的导电材料的电镀方法。 在用于电镀通孔的典型配置中，存在与形成通孔的孔相邻但在其外部的导电材料的第一区域，以及在孔内部的导电材料的第二区域。 选择第二导电区域作为电镀工艺的阴极。 将结构放置在电镀槽中，将第一电位施加到导电材料的第一区域，并且将第二电位施加到导电材料的第二区域，其中第二电位不同于第一电位。 在这些条件下，材料将镀在导电材料的第二区域上以填充孔。 优选地选择第一电位的值以显着降低电镀槽对导电材料的第一区域进行蚀刻的速率，并且可以用于使材料镀在第一区域上，但是以比 电镀第二导电区域。

公开(公告)号：US5854534A

公开(公告)日：1998-12-29

申请号：US559369

申请日：1995-11-16

申请人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

发明人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H05K1/14 ,  H01L23/52 ,  H01L23/04 ,  H01L23/053 ,  H01L23/34

CPC分类号： H05K1/144 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011

摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.

摘要翻译： 示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。 插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。 电源通过刚性段传送，信号通过薄膜柔性连接器布线，该连接器从插入器基板的上表面延伸到下表面。 旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。 可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为 连接的。 在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。 在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。 还公开了制造单芯片插入件的方法。

公开(公告)号：US5544017A

公开(公告)日：1996-08-06

申请号：US277163

申请日：1994-07-19

申请人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Teruo Murase ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou V. Wang

发明人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Teruo Murase ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou V. Wang

IPC分类号： H01L21/48 ,  H01L23/473 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H05K1/14

CPC分类号： H01L21/486 ,  H01L21/4857 ,  H01L23/473 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0652 ,  H05K1/144 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.

摘要翻译： 公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。 衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。 在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。 这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。 不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。 优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。

公开(公告)号：US5419038A

公开(公告)日：1995-05-30

申请号：US78461

申请日：1993-06-17

申请人： Wen-chou V. Wang ,  Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy

发明人： Wen-chou V. Wang ,  Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy

IPC分类号： H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/46 ,  H05K3/36

CPC分类号： H05K3/4691 ,  H05K2201/0394 ,  H05K3/002 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/467 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate. The sequence of signal planes and dielectric layers at the same location on the substrate form a signal plane set which defines a connector. Contact pads are deposited onto the surface of a final dielectric layer and electrically connect with each via. Wires are used to electrically connect the contact pads of one connector to corresponding contact pads of another connector. A portion of the substrate and dielectric layers not comprising a signal plane set is removed, forming electrical connectors flexibly attached by the plurality of wires.

摘要翻译： 通过在衬底的表面上沉积介电层来制造三维薄膜互连器，在电介质层上沉积导电材料层以形成信号平面，在信号面的表面上沉积电介质层，形成 电介质层中的多个通孔延伸到信号平面，并用导电材料填充通孔以形成通孔。 重复形成信号平面，沉积介电层，形成多个通孔和填充通孔的顺序，直到获得预定数量的信号面和通孔的预定布置。 通孔形成在电介质层中对应于先前电介质层中的预定电连接和通路两者的位置处。 信号面形成在基板上的不同位置。 基板上相同位置处的信号平面和电介质层的顺序形成了限定连接器的信号平面组。 接触焊盘沉积在最终电介质层的表面上并与每个通孔电连接。 电线用于将一个连接器的接触焊盘电连接到另一个连接器的相应接触焊盘。 除去不包括信号平面组的衬底和电介质层的一部分，形成由多个电线柔性附接的电连接器。

公开(公告)号：US06226171B1

公开(公告)日：2001-05-01

申请号：US09227239

申请日：1999-01-08

申请人： Solomon I. Beilin ,  William T. Chou ,  Michael G. Lee ,  David Dung Ngo ,  Michael G. Peters ,  James J. Roman ,  Yasuhito Takahashi

发明人： Solomon I. Beilin ,  William T. Chou ,  Michael G. Lee ,  David Dung Ngo ,  Michael G. Peters ,  James J. Roman ,  Yasuhito Takahashi

IPC分类号： H01G4228

CPC分类号： H01L23/50 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K1/162 ,  H05K3/045 ,  H05K3/388 ,  H05K3/44 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2203/0315 ,  H01L2924/00

摘要： Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.

摘要翻译： 公开了用于增加基板电容器的产量的几个发明特征。 本发明的特征涉及在电容器的主介电层的选定区域周围选择性地放置绝缘层和贴片。 这些绝缘层和缺陷防止某些制造处理步骤在主介电层中产生针孔缺陷。 本发明的特征适合于用于主介电层的任何类型的材料，并且特别适用于阳极化电介质层。

公开(公告)号：US6102710A

公开(公告)日：2000-08-15

申请号：US70493

申请日：1998-04-30

申请人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

发明人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H05K1/14 ,  H01R12/00

CPC分类号： H05K1/144 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011

摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.

摘要翻译： 示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。 插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。 电源通过刚性段布线，信号通过从内插器基板的上表面延伸到下表面的薄膜柔性连接器。 旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。 可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为 连接的。 在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。 在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。 还公开了制造单芯片插入件的方法。

公开(公告)号：US6081026A

公开(公告)日：2000-06-27

申请号：US191755

申请日：1998-11-13

申请人： Wen-chou Vincent Wang ,  Yasuhito Takahashi ,  William T. Chou ,  Michael G. Peters ,  Michael G. Lee ,  Solomon Beilin

发明人： Wen-chou Vincent Wang ,  Yasuhito Takahashi ,  William T. Chou ,  Michael G. Peters ,  Michael G. Lee ,  Solomon Beilin

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L23/552 ,  H05K1/02 ,  H05K1/14 ,  H05K3/20 ,  H01L23/12 ,  H01L23/053

CPC分类号： H01L23/5383 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H05K1/0219 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/144 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/10378 ,  H05K3/20

摘要： An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is a dielectric film with patterned metal on both sides. The two metal layers are interconnected by a through via or post process. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides connected by a through via or post process. The upper power/ground wrap substrate, signal core, and lower power/ground substrate are interconnected as desired using z-connection technology (e.g., solder or conductive ink). The power/ground layers on the upper substrate can be connected to the power/ground layers on the lower substrate by suitable edge connectors. With an integrated circuit chip or chips connected to the upper layer of the top substrate of the power/ground wrap and a printed circuit board or other mounting substrate connected to the bottom layer of the lower substrate of the wrap, the inventive interposer provides a set of high density and electrically isolated signal, power, and ground interconnections.

摘要翻译： 一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。 插入器包括信号芯和外部电源/接地连接外壳。 这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。 信号芯是两侧具有图案化金属的电介质膜。 两个金属层通过通孔或后处理相互连接。 电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。 电源/接地套管的上基板和下基板由具有通过通孔或后工艺连接的两侧上的图案化金属层的电介质膜形成。 上电源/地基封装衬底，信号芯和下电源/接地衬底根据需要使用z连接技术（例如焊料或导电油墨）互连。 上基板上的电源/接地层可以通过合适的边缘连接器连接到下基板上的电源/接地层。 通过将集成电路芯片或芯片连接到电源/接地外壳的顶部基板的上层，以及连接到包装的下基板的底层的印刷电路板或其它安装基板，本发明的插入件提供一组 高密度和电隔离的信号，电源和接地互连。

公开(公告)号：US5891354A

公开(公告)日：1999-04-06

申请号：US687723

申请日：1996-07-26

申请人： Michael G. Lee ,  Solomon I. Beilin ,  William T. Chou ,  Michael G. Peters ,  Wen-chou Vincent Wang

发明人： Michael G. Lee ,  Solomon I. Beilin ,  William T. Chou ,  Michael G. Peters ,  Wen-chou Vincent Wang

IPC分类号： H01L21/78 ,  H01L23/482 ,  H05K3/00 ,  B44C1/22 ,  H05K3/06

CPC分类号： H01L21/30604 ,  H01L21/78 ,  H01L23/4822 ,  H01L24/01 ,  H01L2924/01029 ,  H05K3/0017

摘要： Methods of wet etching through a silicon substrate using composite etch-stop layers are disclosed. In one embodiment, the composite etch stop comprises a layer of silicon dioxide and a layer of polyimide.

摘要翻译： 公开了通过使用复合蚀刻停止层的硅衬底进行湿蚀刻的方法。 在一个实施例中，复合蚀刻停止件包括二氧化硅层和聚酰亚胺层。