公开(公告)号：US20240304272A1

公开(公告)日：2024-09-12

申请号：US18330117

申请日：2023-06-06

申请人： SK hynix Inc.

发明人： Yoon Jae SHIN ,  Doo Hyun SON

IPC分类号： G11C29/46 ,  G11C7/02 ,  G11C29/12

CPC分类号： G11C29/46 ,  G11C7/02 ,  G11C29/12005

摘要： An electronic device includes a monitoring signal generation circuit configured to receive an internal voltage to generate a monitoring signal, based on a voltage selection signal in a test mode, and an internal voltage drive circuit configured to receive the internal voltage and monitoring signal from the monitoring signal generation circuit and drive the internal voltage to compensate for the monitoring signal when the monitoring signal is distorted according to a leakage current in the test mode.

公开(公告)号：US12046675B2

公开(公告)日：2024-07-23

申请号：US18234043

申请日：2023-08-15

申请人： Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Dinesh Maheshwari ,  Yuniarto Widjaja

IPC分类号： H10B12/00 ,  H01L27/12 ,  H01L29/78 ,  G06F11/10 ,  G11C7/02 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/12 ,  G11C29/52

CPC分类号： H01L29/7841 ,  H01L27/1211 ,  H10B12/20 ,  G06F11/1068 ,  G11C7/02 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/12 ,  G11C29/52 ,  H01L29/785

摘要： A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

公开(公告)号：US11984172B2

公开(公告)日：2024-05-14

申请号：US17536438

申请日：2021-11-29

申请人： Micron Technology, Inc.

发明人： Patrick Robert Khayat ,  James Fitzpatrick ,  AbdelHakim S. Alhussien ,  Sivagnanam Parthasarathy

IPC分类号： G11C16/34 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC分类号： G11C16/3431 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

摘要： A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.

公开(公告)号：US11875846B2

公开(公告)日：2024-01-16

申请号：US17534907

申请日：2021-11-24

申请人： Micron Technology, Inc.

发明人： James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Patrick Robert Khayat ,  AbdelHakim S. Alhussien

IPC分类号： G11C16/26 ,  G11C29/12 ,  G11C29/44 ,  G11C11/56 ,  G11C29/14 ,  G06N20/00 ,  G11C7/02 ,  G11C29/38 ,  G06F18/214

CPC分类号： G11C11/5642 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C29/12005 ,  G11C29/14 ,  G11C29/38

摘要： A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

公开(公告)号：US11862234B2

公开(公告)日：2024-01-02

申请号：US17457077

申请日：2021-12-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yoon-Joo Eom ,  Seungjun Bae ,  Hye Jung Kwon ,  Young-Ju Kim

IPC分类号： G11C7/20 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/14 ,  G11C7/02 ,  G11C29/50 ,  G11C11/4072 ,  G11C29/02 ,  G11C7/10 ,  G11C5/14

CPC分类号： G11C11/4093 ,  G11C5/147 ,  G11C7/02 ,  G11C7/1069 ,  G11C7/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C29/028 ,  G11C29/50 ,  G11C29/021 ,  G11C29/023 ,  G11C2207/2254

摘要： A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US20230377632A1

公开(公告)日：2023-11-23

申请号：US18203511

申请日：2023-05-30

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC分类号： G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

CPC分类号： G11C11/4093 ,  G11C11/4096 ,  G06F11/1048 ,  G11C7/02 ,  G11C29/52 ,  G11C2029/0411

摘要： Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US11756616B2

公开(公告)日：2023-09-12

申请号：US17522959

申请日：2021-11-10

申请人： FUJITSU LIMITED

发明人： Hiroshi Nakao ,  Masayuki Hiromoto ,  Hisanao Akima ,  Teruo Ishihara ,  Takuji Yamamoto

IPC分类号： G11C7/02 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038

摘要： A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.

公开(公告)号：US11715529B2

公开(公告)日：2023-08-01

申请号：US17689300

申请日：2022-03-08

申请人： KIOXIA CORPORATION

发明人： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC分类号： G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

CPC分类号： G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G11C7/02 ,  G11C7/106 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G06F2205/067 ,  G11C16/0483 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/00

摘要： A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US11705195B2

公开(公告)日：2023-07-18

申请号：US17555005

申请日：2021-12-17

申请人： Micron Technology, Inc.

发明人： Zhongyuan Lu ,  Robert J. Gleixner

IPC分类号： G11C7/02 ,  G11C13/00

CPC分类号： G11C13/004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/15

摘要： The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to count a number of program operations performed on the memory cells of the memory during operation of the memory, and increase a magnitude of a current used to sense a data state of the memory cells of the memory upon the count of the number of program operations reaching a threshold count.

公开(公告)号：US11621030B2

公开(公告)日：2023-04-04

申请号：US17568656

申请日：2022-01-04

申请人： Rambus Inc.

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G11C11/34 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.