公开(公告)号：US20240355898A1

公开(公告)日：2024-10-24

申请号：US18760032

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Lun Min ,  Chang-Miao Liu ,  Xu-Sheng Wu

IPC分类号： H01L29/49 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76834 ,  H01L21/823468 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

公开(公告)号：US20240355730A1

公开(公告)日：2024-10-24

申请号：US18761397

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jia-En Lee ,  Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang

IPC分类号： H01L23/522 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5228 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L28/24

摘要： Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

公开(公告)号：US20240332089A1

公开(公告)日：2024-10-03

申请号：US18741998

申请日：2024-06-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/823468 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/31155 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78696

摘要： Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US12100767B2

公开(公告)日：2024-09-24

申请号：US17669317

申请日：2022-02-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Ta Wu ,  Chii-Ming Wu ,  Shiu-Ko Jangjian ,  Kun-Tzu Lin ,  Lan-Fang Chang

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/7856 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/28114 ,  H01L21/28158 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/495 ,  H01L29/513

摘要： A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

公开(公告)号：US20240304449A1

公开(公告)日：2024-09-12

申请号：US18665199

申请日：2024-05-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Te-Yang Lai ,  Chun-Yen Peng ,  Sai-Hooi Yeong ,  Chi On Chui

IPC分类号： H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/3115 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/513 ,  H01L21/823431

摘要： A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

公开(公告)号：US12068195B2

公开(公告)日：2024-08-20

申请号：US18330466

申请日：2023-06-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/00 ,  H01L2924/0002

摘要： The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US20240274594A1

公开(公告)日：2024-08-15

申请号：US18426241

申请日：2024-01-29

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Michael A. Smith

IPC分类号： H01L27/02 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L25/065 ,  H10B80/00

CPC分类号： H01L27/0207 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823864 ,  H01L25/0657 ,  H10B80/00 ,  H01L2225/06541

摘要： A semiconductor device including a substrate; a plurality of active regions that are disposed on the substrate and that are parallelly aligned; a plurality of first type of trench isolations having a first top critical dimension (CD), each of the plurality of the first type of trench isolations including sidewalls that taper towards one another along a depth direction; and a plurality of second type of trench isolations having a second top CD, the second top CD being larger than the first top CD and each of the plurality of the second type of trench isolations having a flat bottom trench surface.

公开(公告)号：US12062543B2

公开(公告)日：2024-08-13

申请号：US17869707

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Min Hsiao ,  Chien-Wen Lai ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Shih-Ming Chang ,  Yung-Sung Yen ,  Yu-Chen Chang

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3115

CPC分类号： H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

摘要： Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US12027425B2

公开(公告)日：2024-07-02

申请号：US17877221

申请日：2022-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/823468 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/31155 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78696

摘要： Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US12020987B2

公开(公告)日：2024-06-25

申请号：US17885149

申请日：2022-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Hsien Lin ,  Chang-Ching Yeh

IPC分类号： H01L21/8234 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

CPC分类号： H01L21/823431 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31155 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/42392

摘要： A method includes forming a fin structure over a substrate; forming a gate structure over the substrate and crossing the fin structure, wherein the gate structures comprises a gate electrode and a hard mask layer over the gate electrode; forming gate spacers on opposite sidewalls of the gate structure; performing an ion implantation process to form doped regions in the hard mask layers of the gate structure and in the gate spacers, wherein the ion implantation process is performed at a tilt angle; etching portions of the fin structure exposed by the gate structure and the gate spacers to form recesses in the fin structure; and forming source/drain epitaxial structures in the recesses.