公开(公告)号：US10923399B2

公开(公告)日：2021-02-16

申请号：US15885564

申请日：2018-01-31

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Deyuan Xiao ,  Guo Qing Chen ,  Roger Lee

IPC分类号： H01L21/782 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

摘要： A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

公开(公告)号：US10276514B1

公开(公告)日：2019-04-30

申请号：US15866472

申请日：2018-01-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Rung-De Wang ,  Chen-Hsun Liu ,  Chin-Yu Ku ,  Te-Hsun Pang ,  Chia-Hua Wang ,  Pei-Shing Tsai ,  Po-Chang Lin

IPC分类号： H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/782 ,  H01L21/784 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L21/8238

摘要： A semiconductor structure includes a semiconductor device, a first seal ring, a second seal ring, and a plurality of through semiconductor vias (TSV). The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and is adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and is adjacent to edges of the second surface. The TSVs penetrate through the semiconductor device and physically connect the first seal ring and the second seal ring.

公开(公告)号：US10211372B1

公开(公告)日：2019-02-19

申请号：US15939909

申请日：2018-03-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jin Hwan Kim ,  Sung Joon Kim ,  Su Hyun Jo ,  Seung Hwan Lee ,  Tae Sung Jang

IPC分类号： H01L21/78 ,  H01L33/38 ,  H01L27/15 ,  H01L33/44 ,  H01L23/544 ,  H01L21/784 ,  H01L21/782

摘要： A semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, sequentially stacked on a substrate along a first direction, and including an exposed region exposing the first conductivity-type semiconductor layer. A first contact electrode is in the exposed region, a second contact electrode is on the second conductivity-type semiconductor layer, and an insulating layer covers the light emitting structure. Separate electrode pads penetrate the insulating layer to be electrically connected to the first contact electrode and the second contact electrode. A side surface of at least one of the first and second electrode pads may extend to be coplanar with a side surface of the substrate along the first direction.

公开(公告)号：US20190013243A1

公开(公告)日：2019-01-10

申请号：US16132040

申请日：2018-09-14

申请人： Plasma-Therm LLC

发明人： Chris Johnson ,  David Johnson ,  Linnell Martinez ,  David Pays-Volard ,  Rich Gauldin ,  Russell Westerman ,  Gordon M. Grivna

IPC分类号： H01L21/78 ,  H01L21/67 ,  H01J37/32 ,  H01L21/782 ,  H01L21/687 ,  H01L21/683 ,  H01L21/68 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/677

摘要： The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

公开(公告)号：US09564366B2

公开(公告)日：2017-02-07

申请号：US14974840

申请日：2015-12-18

申请人： Plasma-Therm LLC

发明人： Linnell Martinez ,  David Pays-Volard ,  Chris Johnson ,  David Johnson ,  Russell Westerman ,  Gordon M. Grivna

IPC分类号： H01L21/78 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  H01L21/782 ,  H01J37/32 ,  H01L21/68 ,  H01L21/311 ,  H01L21/677

CPC分类号： H01L21/78 ,  H01J37/321 ,  H01J37/32155 ,  H01J37/32422 ,  H01J37/32623 ,  H01J37/32642 ,  H01J37/32651 ,  H01J37/32724 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/67011 ,  H01L21/67069 ,  H01L21/67739 ,  H01L21/68 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/68735 ,  H01L21/68742 ,  H01L21/782 ,  H01L2221/68327 ,  Y10S414/139

摘要： The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

摘要翻译： 本发明提供了一种等离子体切割基板的方法。 该方法包括提供具有壁的处理室; 提供与处理室的壁相邻的等离子体源; 在处理室内提供工件支撑; 将基板放置在框架上的支撑膜上以形成工件工件; 将工件装载到工件支架上; 提供设置在工件上方的盖环; 通过等离子体源产生等离子体; 并通过产生的等离子体蚀刻工件。

公开(公告)号：US09245804B2

公开(公告)日：2016-01-26

申请号：US13967084

申请日：2013-08-14

申请人： NXP B.V.

发明人： Christian Zenz ,  Hartmut Buenning ,  Leonardus Antonius Elisabeth Van Gemert ,  Tonny Kamphuis ,  Sascha Moeller

IPC分类号： H01L21/44 ,  H01L21/82 ,  H01L21/782 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/488 ,  H01L21/50 ,  H01L21/56 ,  H01L21/683 ,  H01L29/06 ,  H01L23/00

CPC分类号： H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

摘要： Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (θ) of tooling impact upon a vertical face the semiconductor device.

摘要翻译： 与示例性实施例一致，存在半导体器件，其中有源器件具有正面和背面; 总体厚度的半导体器件包括具有限定在前侧表面上的电路的有源器件，前侧表面具有区域。 有源器件的背面具有有源器件厚度的部分深度和大约部分深度的宽度的凹部，在垂直边缘处围绕有源器件的凹部。 在有源器件的背面具有厚度的保护层，该保护材料的面积大于第一区域并具有间隔距离。 垂直边缘具有填充与垂直边缘齐平的凹部的保护层。 保护材料的间隔距离是半导体器件厚度和在半导体器件的垂直面上的工具冲击的角度（＆amp;）的切线的函数。

公开(公告)号：US09053980B2

公开(公告)日：2015-06-09

申请号：US13364845

申请日：2012-02-02

申请人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

发明人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

IPC分类号： H01L27/12 ,  H01L21/782 ,  H01L21/84

CPC分类号： H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

摘要翻译： 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件用于光子和电子器件，其中每个晶片的至少一部分结合在一起 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US20140138855A1

公开(公告)日：2014-05-22

申请号：US13967164

申请日：2013-08-14

申请人： NXP B.V.

发明人： Leonardus Antonius Elisabeth VAN GEMERT ,  Hartmut BUENNING ,  Tonny KAMPHUIS ,  Sascha MOELLER ,  Christian ZENZ

IPC分类号： H01L21/782 ,  H01L23/00

CPC分类号： H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

摘要： Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die. Each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.

摘要翻译： 与示例性实施例一致，存在用于组装晶片级芯片尺寸处理（WLCSP）晶片的方法; 晶片具有顶侧表面和背面表面，以及在顶侧表面上具有电触头的多个器件裸片。 该方法包括对晶片的背面进行背面研磨至厚度。 在晶片的背面上模制厚度保护层。 将晶片安装在锯片上; 沿着多个器件裸片的锯条，晶片被锯切，锯切发生在第一切口的刀片和背面晶片厚度的深度上。 再次，晶片沿着多个器件裸片的锯条被锯切，锯切发生在第二切口的刀片上，第二切口比第一切口窄，并锯切到保护层厚度的深度。 将多个器件裸片分离为单个器件管芯。 每个单独的器件管芯在背面具有保护层，保护层具有与单独器件管芯的垂直边缘的间隔距离。

公开(公告)号：US20140110842A1

公开(公告)日：2014-04-24

申请号：US13967084

申请日：2013-08-14

申请人： NXP B.V.

发明人： Christian ZENZ ,  Hartmut BUENNING ,  Leonardus Antonius Elisabeth VAN GEMERT ,  Tonny KAMPHUIS ,  Sascha MOELLER

IPC分类号： H01L21/782 ,  H01L23/498

CPC分类号： H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

摘要： Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (θ) of tooling impact upon a vertical face the semiconductor device.

摘要翻译： 与示例性实施例一致，存在半导体器件，其中有源器件具有正面和背面; 总体厚度的半导体器件包括具有限定在前侧表面上的电路的有源器件，前侧表面具有区域。 有源器件的背面具有有源器件厚度的部分深度和大约部分深度的宽度的凹部，在垂直边缘处围绕有源器件的凹部。 在有源器件的背面具有厚度的保护层，该保护材料的面积大于第一区域并具有间隔距离。 垂直边缘具有填充与垂直边缘齐平的凹部的保护层。 保护材料的间隔距离是半导体器件厚度和在半导体器件的垂直面上的工具冲击的角度（＆amp;）的切线的函数。

公开(公告)号：US20130203238A1

公开(公告)日：2013-08-08

申请号：US13817112

申请日：2011-09-20

申请人： Akira Tamenori

发明人： Akira Tamenori

IPC分类号： H01L21/782

CPC分类号： H01L21/782 ,  H01L21/67092 ,  H01L21/78 ,  H01L29/66348

摘要： Ineffective chips are formed in the circumference of a semiconductor wafer and effective chips are formed in a region surrounded by the ineffective chips. Dicing lines partition the effective chips and the ineffective chips. Polyimide is formed on an outer circumferential portion of the semiconductor wafer with a predetermined width from an outer circumferential end of the semiconductor wafer such that the polyimide continuously covers the ineffective chips from the outer circumferential end of the semiconductor wafer to the inside and continuously covers a portion which is a predetermined distance away from the outer circumferential end of the semiconductor wafer to the effective chip in the dicing line interposed between the ineffective chips. A metal film is formed on the front electrode formed on the effective chips by plating. The semiconductor wafer is cut into semiconductor chips along the dicing lines by a blade.

摘要翻译： 在半导体晶片的圆周上形成无效的芯片，并且在由无效芯片包围的区域中形成有效的芯片。 切割线划分有效芯片和无效芯片。 聚酰亚胺从半导体晶片的外周端以规定的宽度形成在半导体晶片的外周部上，使得聚酰亚胺从半导体晶片的外周端向内部连续地覆盖无效的芯片，并连续地覆盖 部分，其距离半导体晶片的外周端预定距离到插入在无效芯片之间的切割线中的有效芯片。 通过电镀在形成在有效芯片上的前电极上形成金属膜。 通过刀片将半导体晶片沿着切割线切割成半导体芯片。