公开(公告)号：WO2014112954A8

公开(公告)日：2015-09-03

申请号：PCT/SG2014000024

申请日：2014-01-21

Applicant: SEN AMLAN ,  LIM SHOA-SIONG RAYMOND

Inventor： SEN AMLAN ,  LIM SHOA-SIONG RAYMOND

IPC: H01L23/12 ,  H01L21/50 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L23/49827 ,  H01L21/54 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/145 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K1/0366 ,  H05K1/111 ,  H05K2201/0195 ,  Y10T29/303 ,  Y10T29/49167 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: A method of forming a substrate (10) for semiconductor packaging and a substrate (10) for semiconductor packaging are provided. The method includes providing a carrier (12) and forming a plurality of external pads (14) on the carrier (12), the external pads (14) formed on the carrier (12) defining a first conductive layer. A molding operation is performed to form a first insulating layer (20) on the carrier (12) with a molding compound (22). The first conductive layer is embedded in the first insulating layer (20). One or more of a plurality of bond pads (30), a plurality of conductive traces (32) and a plurality of microvias (56) are formed on the first conductive layer, the one or more of the bond pads (30), the conductive traces (32) and the microvias (56) formed on the first conductive layer defining a second conductive layer.

Abstract translation: 提供一种形成用于半导体封装的衬底（10）和用于半导体封装的衬底（10）的方法。 该方法包括提供载体（12）并在载体（12）上形成多个外部焊盘（14），形成在载体（12）上的形成第一导电层的外部焊盘（14）。 进行成型操作以在模具（22）上形成载体（12）上的第一绝缘层（20）。 第一导电层嵌入第一绝缘层（20）中。 多个接合焊盘（30）中的一个或多个，多个导电迹线（32）和多个微孔（56）形成在第一导电层上，一个或多个接合焊盘（30）， 导电迹线（32）和形成在第一导电层上的微孔（56）限定第二导电层。

公开(公告)号：WO2010059133A1

公开(公告)日：2010-05-27

申请号：PCT/SG2009/000439

申请日：2009-11-20

Applicant: ADVANPACK SOLUTIONS PRIVATE LIMITED ,  LIM, Shoa Siong ,  LIM, Kian, Hock

Inventor： LIM, Shoa Siong ,  LIM, Kian, Hock

IPC: H01L23/24

CPC classification number: H01L23/24 ,  H01L23/40 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.

Abstract translation: 公开了一种半导体封装及其制造方法。 半导体封装包括器件载体和加强结构。 装置载体包括至少一个绝缘层和至少限定至少一个迹线布局单元的导电层。 加强件结构设置在装置载体上，围绕至少一个迹线布局单元的周边。 加强件结构远离所述至少一个迹线布局单元的周边设置，与所述器件载体形成空腔。 加强结构的形状和配置增强了半导体封装的强度，阻碍了半导体封装的挠曲。

公开(公告)号：WO2010053454A1

公开(公告)日：2010-05-14

申请号：PCT/SG2009/000413

申请日：2009-11-09

Applicant: ORION SYSTEMS INTEGRATION PTE LTD ,  CHEW, Hwee, Seng ,  ONG, Chee, Kian ,  LIM, Kian, Hock ,  SEN, Amlan ,  LIM, Shoa, Siong

Inventor： CHEW, Hwee, Seng ,  ONG, Chee, Kian ,  LIM, Kian, Hock ,  SEN, Amlan ,  LIM, Shoa, Siong

IPC: H01L21/50 ,  H01L21/68 ,  H01L21/98 ,  B23K1/19 ,  H01L21/683 ,  B23K101/40

CPC classification number: B23K1/0016 ,  B23K1/203 ,  B23K2201/40 ,  H01L21/683 ,  H01L21/6838 ,  H01L21/68707 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68354 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7515 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/755 ,  H01L2224/75501 ,  H01L2224/7565 ,  H01L2224/757 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81121 ,  H01L2224/8115 ,  H01L2224/8116 ,  H01L2224/8117 ,  H01L2224/8118 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/3841 ,  Y10T29/41 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating a flip-chip semiconductor package comprising processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. The semiconductor chip is heated to a chip process temperature. The chip process temperature melts solder portions on the bump structures. The substrate is heated to a substrate process temperature, wherein said substrate process temperature may be different to the chip process temperature. The semiconductor chip is spatially aligned in relation to the substrate to correspondingly align the bump structures in relation to the bond pads. The semiconductor chip is displaced towards the substrate to abut the bump structures with the bond pads to thereby form bonds there between. A system for performing the above method is also disclosed.

Abstract translation: 一种用于制造倒装芯片半导体封装的方法，包括处理半导体器件，例如半导体芯片并处理器件载体，例如衬底。 半导体器件包括在其表面上形成的凸块结构。 衬底包括形成在其表面上的接合焊盘。 将半导体芯片加热至芯片工艺温度。 芯片工艺温度熔化凸块结构上的焊接部分。 将衬底加热到​​衬底工艺温度，其中所述衬底工艺温度可能与芯片工艺温度不同。 半导体芯片相对于衬底在空间上对准，以相对于接合焊盘相应地对准凸块结构。 半导体芯片朝向衬底移位，以与接合焊盘邻接凸块结构，从而在其间形成结合。 还公开了用于执行上述方法的系统。

公开(公告)号：WO2010056210A1

公开(公告)日：2010-05-20

申请号：PCT/SG2009/000428

申请日：2009-11-17

Applicant: ADVANPACK SOLUTIONS PRIVATE LIMITED ,  LIM, Shoa, Siong ,  LIM, Kian, Hock

Inventor： LIM, Shoa, Siong ,  LIM, Kian, Hock

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/60

CPC classification number: H01L23/5385 ,  H01L21/4846 ,  H01L23/49861 ,  H01L23/552 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor substrate including a carrier, a first conductive layer and a second conductive layer is disclosed. The carrier has a first surface, a second surface, and a concave portion used for receiving a semiconductor element. The first conductive layer is embedded in the first surface and forms a plurality of electric-isolated package traces. The second conductive layer is embedded in the second surface and electrically connected to the first conductive layer. The semiconductor substrate can be applied to a semiconductor package for carrying a semiconductor chip, and combined with a filling structure for fixing the chip' Furthermore, a plurality of the semiconductor substrates can be stacked and connected via adhesive layers, so as to form a semiconductor device with a complicated structure.

Abstract translation: 公开了一种包括载体，第一导电层和第二导电层的半导体衬底。 载体具有第一表面，第二表面和用于接收半导体元件的凹部。 第一导电层嵌入第一表面并形成多个电隔离封装迹线。 第二导电层嵌入第二表面并电连接到第一导电层。 半导体衬底可以应用于用于承载半导体芯片的半导体封装，并且与用于固定芯片的填充结构组合。此外，多个半导体衬底可以通过粘合剂层堆叠和连接，以形成半导体 设备结构复杂。

公开(公告)号：WO2010053452A1

公开(公告)日：2010-05-14

申请号：PCT/SG2009/000408

申请日：2009-11-06

Applicant: ADVANPACK SOLUTIONS PRIVATE LIMITED ,  LIM, Shoa Siong ,  LIM, Kian Hock

Inventor： LIM, Shoa Siong ,  LIM, Kian Hock

IPC: H01L23/498

CPC classification number: H01L23/49861 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/28 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package, a method for manufacturing the semiconductor package, a trace substrate and a method for manufacturing the trace substrate are provided. The semiconductor package includes a trace substrate, a chip and a plurality of wires. The trace substrate includes a plurality of trace, a plurality of conductive studs, a plurality of traces pads and a trace modling compound. The conductive studs are formed on the lower surfaces of the traces. The trace modling compound encapsulates the conductive studs and the trace, and exposes the lower surfaces of the conductive studs and the upper surfaces of the traces. The chip is disposed on the trace substrate, and the wires electrically connect the chip and the trace pads. The trace pads are not overlapping to the conductive studs.

Abstract translation: 提供了一种半导体封装，半导体封装的制造方法，迹线衬底和用于制造迹线衬底的方法。 半导体封装包括迹线衬底，芯片和多根电线。 迹线衬底包括多个迹线，多个导电柱，多个迹线焊盘和迹线模塑化合物。 导电螺柱形成在轨迹的下表面上。 轨迹模拟化合物封装导电螺柱和轨迹，并露出导电螺柱的下表面和迹线的上表面。 芯片设置在迹线基板上，并且电线将芯片和迹线焊盘电连接。 迹线焊盘不与导电螺柱重叠。