Abstract:
This process comprises: placing (70) chips in preset locations by attracting a transfer layer of the chip using a pad, the attractive force between the transfer layer and the pad being a force chosen from the group composed of a magnetic force, an electrostatic force and an electromagnetic force; and bonding (74) the chips thus placed on respective receiving zones of an active side of a receiver substrate, this bonding comprising: preparing (30, 62, 72) bonding sides of the chips and the receiving zones so that they are able to bond without adhesive, then in step c), bringing (78) each bonding side into direct contact with its respective receiving zone and thus bonding the chips to the receiver substrate without adhesive.
Abstract:
A method for obtaining metal-to-metal contact between a bonding surface of a metallic bonding area and a second metal surface is disclosed. The method comprises the steps of : - coating said bonding surface of said metallic bonding area with a chemical composition that forms a self-assembled monolayer on said bonding surface of said metallic bonding area, and - bonding said second metal surface on said coated bonding surface through said selfassembled monolayer. The combination of the coating step and the bonding step result in a metal to metal contact between the bonding surface of he metallic bonding area and the second metal surface. The metallic bonding area can be a semiconductor bond pad, e.g. of a semiconductor device.
Abstract:
In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).
Abstract:
According to the invention, the first metal layer (107) is soldered to the second metal layer (102) using a soldering material (104), whereby only a portion of the first metal layer (107) is transformed into one or more intermetallic phases (122) with the soldering material that is used.
Abstract:
According to the invention, the first metal layer (107) is soldered to the second metal layer (102) using a soldering material (104), whereby only a portion of the first metal layer (107) is transformed into one or more intermetallic phases (122) with the soldering material that is used.
Abstract:
The invention relates to a metallization (40) (and a semiconductor wafer (10) having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump. The method for producing a metallization (40) for at least one contact pad (20) according to the invention comprises the following process steps: applying at least one contact pad (20) to a substrate (10), applying a barrier layer (30) to the top side of the at least one contact pad (20) and applying a metallization (40) to the top side of the barrier layer (30), the barrier layer (30) and the metallization (40) being applied by means of physical separation and the metallization (40) being designed as a layer structure having two multiple alternating metallization layers (41, 42), wherein the first metallization layer (41) is made of nickel or an Ni alloy having a layer thickness of less than 500 nm and the second metallization layer (42) is made of a material that is different than nickel and is electrically conductive.
Abstract:
Auf mindestens einem externen Chip-Metallkontakt des elektronischen Chips ist eine Vielzahl von Nanoröhren aufgebracht zum Kontaktieren des elektronischen Chips mit einem weiteren elektronischen Chip.
Abstract:
Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the substrate, or in one or more layers deposited on the surface of the sacrificial substrate. Each spring contact element has a base end portion, a contact end portion, and a central body portion. The contact end portion is offset in the z-axis (at a different height) than the central body portion. The base end portion is preferably offset in an opposite direction along the z-axis from the central body portion. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the sacrificial substrate. The spring contact elements are suitably mounted by their base end portions to corresponding terminals on an electronic component, such as a space transformer or a semiconductor device, whereupon the sacrificial substrate is removed so that the contact ends of the spring contact elements extend above the surface of the electronic component. In an exemplary use, the spring contact elements are thereby disposed on a space transformer component of a probe card assembly so that their contact ends effect pressure connections to corresponding terminals on another electronic component, for the purpose of probing the electronic component.
Abstract:
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
Abstract:
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung einer Metallisierung für mindestens ein Kontaktpad und einen Halbieiterwafer mit Metallisierung für mindestens ein Kontaktpad. Es ist Aufgabe der voriiegenden Erfindung, eine Metallisierung (bzw. einen Halbleiterwafer mit entsprechender Metallisierung) und ein Verfahren zu deren Herstellung anzugeben, die einerseits mittels physikalischer Gasphasenabscheidung (Trockenabscheidung) herstellbar sind und andererseits eine ausreichend hohe Adhäsion eines Lot-Bumps gewährleisten. Das erfindungsgemäße Verfahren zur Herstellung einer Metallisierung (40) für mindestens ein Kontaktpad (20) weist folgende Verfahrensschritte auf: Aufbringen mindestens eines Kontaktpads (20) auf ein Substrat (10), Aufbringen einer Barriereschicht (30) auf die Oberseite des mindestens einen Kontaktpads (20), und Aufbringen einer Metallisierung (40) auf die Oberseite der Barriereschicht (30), dadurch gekennzeichnet, dass die Barriereschicht (30) und die Metallisierung (40) mittels physikalischer Abscheidung aufgebracht werden und dass die Metallisierung (40) als Schichtstruktur zweier, mehrfach alternierender Metallisierungsschichten (41, 42) ausgebildet wird, wobei die erste Metallisierungsschicht (41) aus Nickel oder eine Ni-Legierung mit einer Schichtdicke kleiner als 500 nm und die zweite Metallisierungsschicht (42) aus einem von Nickel verschiedenen, elektrisch leitfähigen Material ausgebildet wird.