公开(公告)号：EP1874102A1

公开(公告)日：2008-01-02

申请号：EP07012401.1

申请日：2007-06-25

Applicant: Ibiden Co., Ltd.

Inventor： Tanaka, Hironori

IPC: H05K1/16 ,  H01L23/50

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon includes: a first capacitor formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor built along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area. The wiring board further includes: lines that electrically connect a power pad for supplying power to the IC chip and a ground pad for grounding the IC chip to either the first lower electrode or the second lower electrode and to the first upper electrode or the second upper electrode.

Abstract translation: 具有内置电容器的布线板，其具有多层布线结构并且能够安装IC芯片，其上包括：第一电容器，其形成为使得第一电容器和第一上电极之间的重叠区域设置在 第一电介质层是预定区域; 以及第二电容器，其沿与第一电介质层相同的平面构成，并且形成为使得设置在与第一电介质层相同厚度的第二电介质层的各个表面上的第二下电极和第二上电极之间的重叠区域是 与预定区域不同。 所述布线板还包括：将与所述IC芯片供电的功率垫电连接的线路和用于将所述IC芯片接地到所述第一下部电极或所述第二下部电极以及所述第一上部电极或所述第二上部 电极。

公开(公告)号：EP1269808B1

公开(公告)日：2007-08-22

申请号：EP01916828.5

申请日：2001-03-30

Applicant: Dyconex AG

Inventor： SCHMIDT, Walter

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer (11,11') and a prefabricated product (1) are placed between two perforation dies (21,23) or a support and a perforation die. The prefabricated product (1) is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die (21,22), perforation tips of the perforation dies forming microvias for contacting the structures. A surface of the dielectric layer (11,11') or the prefabricated product (1) is configurated or coated to in a manner that the prefabricated product (1) and the dielectric layer (11,11') stick to each other after the pressure has been applied.

公开(公告)号：EP1387367B1

公开(公告)日：2007-01-10

申请号：EP02710342.3

申请日：2002-01-24

Applicant: JSR Corporation

Inventor： ITO, Nobuyuki, c/o JSR CORPORATION ,  MASUKO, Hideaki, c/o JSR CORPORATION ,  HASEGAWA, Satomi, c/o JSR CORPORATION ,  YOSHIMURA, Nakaatsu, c/o JSR CORPORATION

IPC: H01B3/00 ,  H01B3/12 ,  C08K3/22 ,  C08K9/00 ,  H05K1/03 ,  H01G4/20 ,  C08K9/02 ,  C08K9/04

CPC classification number: H01L24/49 ,  C08K9/02 ,  H01L23/145 ,  H01L23/49527 ,  H01L23/49589 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/0101 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/0373 ,  H05K1/162 ,  H05K3/0023 ,  H05K3/4644 ,  H05K3/4673 ,  H05K2201/0209 ,  H05K2201/0218 ,  H05K2201/0239 ,  H05K2201/0257 ,  H05K2201/0326 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/135 ,  H01L2924/00 ,  H01L2224/45099

Abstract: The dielectric-forming composition according to the invention is characterized by consisting of: composite particles for dielectrics in which part or all of the surfaces of inorganic particles with permittivity of 30 or greater are coated with a conductive metal or a compound thereof, or a conductive organic compound or a conductive inorganic material; and (B) a resin component constituted of at least one of a polymerizable compound and a polymer. In addition, another dielectric-forming composition according to the invention is characterized by containing: ultrafine particle-resin composite particles composed of (J) inorganic ultrafine particles with the average particle size of 0.1 mu m or smaller, and (B) a resin component constituted of at least one of a polymerizable compound and a polymer, wherein part or all of the surfaces of the inorganic ultrafine particles (J) are coated with the resin component (B), and the ultrafine particle-resin composite particles contain 20% by weight or more of the inorganic ultrafine particles (J); and inorganic particles with the average particle size of 0.1 to 2 mu m and permittivity of 30 or greater, or inorganic composite particles in which a conductive metal or a compound thereof, or a conductive organic compound or a conductive inorganic material is deposited on the part or all of the surfaces of the inorganic particles.

Abstract translation: 形成电介质组合物雅定到本发明通过由......组成为特征：在其中部分或电介质都具有30或更大的介电常数的无机颗粒的表面的复合颗粒被涂覆有导电金属或它们的化合物，或导电 有机化合物或传导性无机材料; 和（B）的树脂成分构成的聚合性化合物和聚合物中的至少一种制成。 另外，另一种电介质形成用组合物雅鼎的发明是通过含有为特征：（J）具有0.1微米或更小，并且平均粒径的无机超微粒子构成超细颗粒 - 树脂复合粒子（B ）的树脂成分构成的聚合性化合物和聚合物中的至少一种的，worin部分或全部涂有树脂成分（B）的无机超微粒子（J）的表面的，和超细颗粒的树脂复合粒子 含有20％（重量）或更多的无机超微粒子（J）的; 并用0.1〜2微米的平均粒径和30或更大的介电常数，或无机复合颗粒的无机颗粒，其中导电金属或它们的化合物，或导电性有机化合物或导电无机材料沉积在所述部分 或全部的无机颗粒的表面。

公开(公告)号：EP1675448A1

公开(公告)日：2006-06-28

申请号：EP05027058.6

申请日：2005-12-12

Applicant: E.I. du Pont de Nemours and Company

Inventor： Amey, Daniel Irwin, Jr. ,  Banerji, Sounak ,  Borland, William J. ,  McGregor, David Ross ,  Sreeram, Attiganal N. ,  Dietz, Karl Hartmann

IPC: H05K3/46 ,  H05K1/18 ,  H05K1/16

CPC classification number: H05K1/186 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The present invention relates to a power core (600) comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor (410); and at least one planar capacitor laminate (340); wherein at least one planar capacitor laminate (340) serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor (410); and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

Abstract translation: 电源芯（600）技术领域本发明涉及一种功率磁芯（600），包括：至少一个嵌入式表面贴装技术（SMT）离散芯片电容层，包括至少一个嵌入式SMT分立芯片电容器（410）; 和至少一个平面电容器层压板（340）; 其中至少一个平面电容器层叠体（340）用作低电感路径以向至少一个嵌入式SMT分立片式电容器（410）提供电荷; 并且其中所述嵌入式SMT分立片式电容器与所述平面电容层叠体并联连接。

公开(公告)号：EP1675131A1

公开(公告)日：2006-06-28

申请号：EP05257897.8

申请日：2005-12-21

Applicant: E.I. du Pont de Nemours and Company

Inventor： Cox, Sidney G.

IPC: H01B3/30 ,  C08K3/00

CPC classification number: H01L23/49894 ,  B32B7/02 ,  B32B15/08 ,  B32B15/082 ,  B32B15/092 ,  B32B15/095 ,  B32B15/20 ,  B32B27/20 ,  B32B27/281 ,  B32B27/308 ,  B32B2250/40 ,  B32B2264/102 ,  B32B2264/12 ,  B32B2307/20 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2457/08 ,  B32B2457/14 ,  B32B2457/16 ,  C08K3/22 ,  H01B3/30 ,  H01G4/206 ,  H01L27/016 ,  H01L28/55 ,  H01L2224/32225 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309

Abstract: The present invention relates to a dielectric composition comprising: paraelectric filler; and polymer wherein said paraelectric filler has a dielectric constant between 50 and 150.

Abstract translation: 本发明涉及的电介质组合物，包括：对电动填料; 和聚合物worin所述对电填充物具有50和第150个之间的介电常数

公开(公告)号：EP1648207A2

公开(公告)日：2006-04-19

申请号：EP05020896.6

申请日：2005-09-26

Applicant: E.I. du Pont de Nemours and Company

Inventor： Borland, Willima J. ,  Cox, Sidney G. ,  McGregor, David Ross

IPC: H05K1/16 ,  H01G4/40

CPC classification number: H01C17/06533 ,  H01C7/005 ,  H01C17/06586 ,  H01G4/40 ,  H05K1/162 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09763 ,  Y10T29/49155

Abstract: A capacitive/resistive device (101) provides both resistive and capacitive functions. The capacitive/resistive device (101) may be embedded within a layer of a printed wiring board (1000). The capacitive/resistive device (101) comprises a first electrode (110); a dielectric (120) disposed over the first electrode (110); a resistor element (140) formed on and adjacent to the dielectric (120); a conductive trace (145); and a second electrode (130) disposed over the dielectric (120) and in electrical contact with the resistor element (140), wherein the dielectric is disposed between the first electrode (110) and the second electrode (130) and wherein the dielectric (120) comprises a polymer filled with a high dielectric constant powder phase.

Abstract translation: 电容/电阻装置（101）同时提供电阻和电容的功能。 的电容/电阻装置（101）可被嵌入印刷线路板（1000）的一个层内。 的电容/电阻装置（101）包括第一电极（110）; 设置在第一电极（110）的电介质（120）; 一个电阻器元件（140）上形成并邻近所述电介质（120）; 的导电迹线（145）; 和设置在所述电介质（120），并与worin所述电介质是所述第一电极（110）和第二电极（130）之间设置在所述电阻器元件（140）电接触的第二电极（130）和worin所述电介质（ 120）包括填充有具有高介电常数的粉末相的聚合物。

公开(公告)号：EP1038417B1

公开(公告)日：2006-02-15

申请号：EP99970553.6

申请日：1999-10-12

Applicant: MATSUSHITA ELECTRIC WORKS, LTD.

Inventor： FILLION, Arthur, J. ,  KOGAMI, Osamu ,  KURATA, Kanji 2-8 Aza-Furumachi ,  MURRAY, Jeffrey, A. ,  SMITH, Terrence, A.

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0256 ,  H05K1/162 ,  H05K3/0052 ,  H05K2201/0355 ,  H05K2201/09154 ,  H05K2201/09309 ,  H05K2203/0228 ,  H05K2203/0346 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T428/24777 ,  Y10T428/24917

Abstract: The present invention provides thin-laminate panels (i.e., thin-laminate panels (2) having dielectric layers (8) about 0.006 inches (0.15 mm) or less and conductive layers (6) on either side of the dielectric layer (8)), wherein the edges of the dielectric layers of the panels are free of conductive material, such as copper. The thin-laminate panel is designed to provide necessary capacitance for all or a substantial number of the integrated circuits to be formed thereon. The thin-laminate panels of the present invention may be tested for manufacturing defects, such as short circuits, before further processing of the panels to produce PCBs. 'Finishing' methods for shearing sheets of unfinished thin-laminate into the finished thin-laminate panels of the present invention in a manner that does not cause smearing of the conductive material onto the dielectric layer are also provided.

公开(公告)号：EP1617557A1

公开(公告)日：2006-01-18

申请号：EP05254375.8

申请日：2005-07-13

Applicant: Nihon Dempa Kogyo, Co., Ltd.

Inventor： Matsumoto, Takashi, c/o Nihon Dempa Kogyo Co., Ltd

IPC: H03B5/36

CPC classification number: H05K1/0233 ,  H03B5/362 ,  H05K1/025 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/1003 ,  H05K2201/1006

Abstract: The present invention has a configuration such that in a multiplier crystal oscillator wherein a multilayer board having earthing metal films on both principal planes of an intermediate board, and mount boards laminated on both sides thereof, and at least one multiplier LC filter is arranged on one principal plane of the laminated board, an opening is provided in the earthing metal film that is provided on one principal plane of the intermediate board opposed to an arrangement region of the LC filter, and a ground of the intermediate board is exposed. An object of the present invention is to provide a multiplier oscillator wherein particularly the displacement and irregularity of the multiple frequencies serving as the output frequency is prevented, and furthermore spurious oscillations are suppressed.

Abstract translation: 本发明具有这样的结构，即在一个倍增器晶体振荡器中，其中在中间板的两个主平面上具有接地金属膜的多层板和在其两侧上层叠的安装板以及至少一个倍增器LC滤波器被布置在一个 在中间基板的与LC滤波器的配置区域相对的一个主面上设置的接地金属膜上设有开口，中间基板的接地露出。 本发明的一个目的是提供一种乘法器振荡器，其中特别是防止了用作输出频率的多个频率的位移和不规则性，并且进一步抑制了寄生振荡。

公开(公告)号：EP0902048B1

公开(公告)日：2005-11-23

申请号：EP98302799.6

申请日：1998-04-09

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Lee, Yueh-Ling ,  Min, Gary

IPC: C08K3/24 ,  C08K3/22 ,  B32B27/30 ,  B32B27/34 ,  B32B15/08 ,  H05K1/16

CPC classification number: B32B27/08 ,  B32B15/08 ,  B32B15/20 ,  B32B27/20 ,  B32B27/281 ,  B32B27/34 ,  B32B2255/20 ,  B32B2307/204 ,  B32B2379/08 ,  B32B2457/08 ,  B32B2457/16 ,  C08K3/24 ,  H05K1/0346 ,  H05K1/0373 ,  H05K1/162 ,  H05K3/386 ,  H05K3/4611 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  Y10T428/252 ,  Y10T428/2852 ,  Y10T428/2896 ,  Y10T428/31721 ,  C08L79/08

公开(公告)号：EP1349271A3

公开(公告)日：2005-03-09

申请号：EP03006203.8

申请日：2003-03-19

Applicant: Nec Tokin Corporation

Inventor： Arai, Satoshi ,  Ohya, Kazumasa ,  Inoi, Takayuki ,  Saiki, Yoshihiko

IPC: H03H1/00

CPC classification number: H05K1/0233 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/1006 ,  H05K2201/10689

Abstract: In an electronic device supplying a DC power to an LSI chip (20), a noise filter (1) of a distributed constant type, having an input port (2, 3) and an output port (5, 4), is mounted on a circuit board (6). The noise filter (1) reduces high-frequency noise incoming thereto and allows DC current to flow therethrough. The input port (2, 3) is connected to a DC power line (7a) and a ground conductor (8a) on the circuit board (6). The output port (5, 4) is connected to a separate power conductor (7b) and a separate ground conductor (8b) which are connected to the LSI (20) mounted on the circuit board (6). In another embodiment, the LSI (20) is mounted on a different circuit board (17) to which the output port (5, 4) is connected through conductor pins (18, 19) standing on the circuit board (6).

Abstract translation: 在向LSI芯片（20）供应直流电的电子装置中，具有输入端口（2,3）和输出端口（5,4）的分布常数型噪声滤波器（1）安装在 一个电路板（6）。 噪声滤波器（1）降低了进入其中的高频噪声，并允许直流电流流过。 输入端口（2,3）连接到电路板（6）上的DC电源线（7a）和接地导体（8a）。 输出端口（5,4）连接到与安装在电路板（6）上的LSI（20）连接的单独的功率导体（7b）和单独的接地导体（8b）。 在另一个实施例中，LSI（20）通过竖立在电路板（6）上的导体引脚（18,19）安装在与输出端口（5,4）连接的不同电路板（17）上。