公开(公告)号：EP1544320A2

公开(公告)日：2005-06-22

申请号：EP04029929.9

申请日：2004-12-17

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Hegemann, Dirk, Dr. ,  Oehr, Christian, Dr. ,  Müller, Michaela, Dr.

IPC: C23C16/50 ,  C23C16/02 ,  H05K3/28

CPC classification number: C23C16/26 ,  C23C16/0236 ,  H05K3/282 ,  H05K3/3489 ,  H05K2201/0179 ,  H05K2203/095

Abstract: Die Erfindung betrifft ein Verfahren zur Passivierung einer für die Verlötung vorgesehenen Endoberfläche im Plasma sowie eine verbesserte passivierte Endoberfläche, die durch dieses Verfahren erhältlich ist.

Abstract translation: 在制造微电子部件的过程中，表面被赋予被动并且适合于焊接工艺。 在存在气体等离子体的情况下，表面被去氧化清洁并在单一过程中被被动涂层剂覆盖。 被动涂层可以通过焊接工艺去除。 还要求保护的是合适的微电子元件。

公开(公告)号：EP1518275A2

公开(公告)日：2005-03-30

申请号：EP03735449.5

申请日：2003-05-23

Applicant: SCHOTT AG

Inventor： LEIB, Jürgen ,  MUND, Dietrich

IPC: H01L23/66

CPC classification number: C03B19/00 ,  C03C3/083 ,  C03C3/089 ,  C03C4/12 ,  C03C14/006 ,  C03C15/00 ,  C03C17/02 ,  C03C17/34 ,  C03C2214/16 ,  C03C2217/21 ,  C03C2217/77 ,  C03C2218/15 ,  C03C2218/32 ,  C03C2218/328 ,  C03C2218/33 ,  C03C2218/355 ,  C23C14/10 ,  H01L21/02129 ,  H01L21/02145 ,  H01L21/02161 ,  H01L21/02263 ,  H01L21/31616 ,  H01L21/31625 ,  H01L21/50 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/10 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/97 ,  H01L51/5203 ,  H01L51/5237 ,  H01L51/5262 ,  H01L2223/6627 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01P3/003 ,  H01P11/003 ,  H05K3/28 ,  H05K3/467 ,  H05K2201/0179 ,  Y02P40/57 ,  H01L2924/00

Abstract: The invention relates to a method for producing a substrate (1) comprising a conductor assembly (4, 41, 42) that is suitable for use at high frequencies, said substrate having improved high-frequency characteristics. The method comprises the following steps: deposition of a structured glass layer (9, 91, 92, 93, 13) comprising at least one opening (8) above a contact region (71 - 74) by vapour deposition on the substrate (1); and application of at least one conductor structure (100, 111, 112, 113) to the glass layer (9, 91 - 93), which is in electric contact with the contact region (71 - 74).

公开(公告)号：EP1005260A3

公开(公告)日：2004-04-07

申请号：EP99309146.1

申请日：1999-11-17

Applicant: MicroCoating Technologies, Inc.

Inventor： Hunt, Andrew Tye ,  Flanagan, John Scott ,  Neuman, George Andrew

IPC: H05K1/16 ,  H01G4/10 ,  H01G4/08 ,  C23C16/453

CPC classification number: H05K1/162 ,  H01G4/085 ,  H05K3/388 ,  H05K3/467 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309

Abstract: Thin layer capacitors are formed from a first flexible metal layer (402,502), a dielectric layer (404,504) between about 0.03 and about 2 microns deposited thereon, and a second flexible metal layer (406,506) deposited on the dielectric layer (404,504). The first flexible metal layer may either be a metal foil (402), such as a copper, aluminum, or nickel foil, or a metal layer (502) deposited on a polymeric support sheet (501). Depositions of the layers is by or is facilitate by combustion chemical vapor deposition or controlled atmosphere chemical vapor deposition.

公开(公告)号：EP0732713B1

公开(公告)日：2003-10-22

申请号：EP96104179.5

申请日：1996-03-15

Applicant: OMRON CORPORATION

Inventor： Kawai, Wakahiro

IPC: H01G4/33 ,  H01G4/008 ,  H05K1/16

CPC classification number: H01G4/08 ,  H05K1/162 ,  H05K3/102 ,  H05K3/245 ,  H05K3/38 ,  H05K3/383 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09763 ,  Y10T29/43 ,  Y10T29/435

公开(公告)号：EP1154480A3

公开(公告)日：2003-01-29

申请号：EP01304076.1

申请日：2001-05-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Mashino, Naohiro

IPC: H01L23/498 ,  H01L23/50

CPC classification number: H01L23/49822 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/053 ,  H05K1/056 ,  H05K1/141 ,  H05K1/162 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09809 ,  H05K2203/0315

Abstract: A multilayer wiring board (101) comprises: a metal substrate (102) as a core, a condenser dielectric layer (102a) formed to cover the metal layer (102) and a condenser electrode metal layer (104) formed to cover the condenser dielectric layer (102a), so that a condenser is defined by the metal substrate (102), the condenser dielectric layer (102a) and the condenser electrode metal layer (104). The condenser dielectric layer (102a) is provided with a first contact hole (102b) to communicate with the metal substrate (102) and the condenser electrode metal layer (104) is provided with a second contact hole (104b) to communicate with the first contact hole, the diameter of the second contact hole (104b) being larger than that of the first contact hole (102b). An insulating layer (111) is formed on the condenser electrode metal layer (104) and is provided with a via hole to communicate with the metal substrate through the second and first contact holes (102b,104b). A metal substrate contact metal layer (112a) is formed on an inner wall of the via hole, so that the metal substrate contact metal layer (112a) comes into electrical contact with the metal substrate (102).

公开(公告)号：EP1123988A1

公开(公告)日：2001-08-16

申请号：EP00204364.4

申请日：2000-12-07

Applicant: Ga-Tek Inc., d.b.a. Gould Electronics Inc.

Inventor： Wang, Jiangtao ,  Callahan, John ,  Lillie, Dan

IPC: C23C14/02 ,  H05K3/14 ,  C23C28/00

CPC classification number: H05K1/167 ,  C23C2/02 ,  C23C2/26 ,  C23C14/024 ,  C23C14/025 ,  C23C28/321 ,  C23C28/322 ,  C23C28/3225 ,  C23C28/345 ,  C23C28/3455 ,  H05K3/384 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0361 ,  Y10T428/12438

Abstract: A method of applying a metal onto a copper layer, comprising the steps of:

stabilizing a surface of a copper layer by applying a stabilization layer thereto, the stabilization layer comprised of zinc oxide, chromium oxide, nickel, nickel oxide or a combination thereof and having a thickness of between about 5Å and about 70Å; and
vapor depositing a metal selected from the group consisting of aluminum, nickel, chromium, copper, iron, indium, zinc, tantalum, tin, vanadium, tungsten, zirconium, molybdenum and alloys thereof onto the stabilized surface of the copper layer, and a sheet material formed thereby.

Abstract translation: 一种在铜层上施加金属的方法，包括以下步骤：通过向其施加稳定层来稳定铜层的表面，所述稳定层由氧化锌，氧化铬，镍，氧化镍或其组合构成，稳定层由 具有约5安格姆至约70安培之间的厚度; 将从铝，镍，铬，铜，铁，铟，锌，钽，锡，钒，钨，锆，钼及其合金中选出的金属气相沉积在铜层的稳定化表面上， 由此形成的片材。

公开(公告)号：EP1111679A2

公开(公告)日：2001-06-27

申请号：EP00204615.9

申请日：2000-12-18

Applicant: Philips Corporate Intellectual Property GmbH ,  Koninklijke Philips Electronics N.V.

Inventor： Copetti, Carlo, Dr., c/o Philips Corporate ,  Sanders, Frans, c/o Philips Corporate ,  Fleuster, Martin, Dr., c/o Philips Corporate

IPC: H01L27/01 ,  H01L21/70

CPC classification number: H05K1/162 ,  H01L27/016 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/16 ,  H05K1/167 ,  H05K3/388 ,  H05K3/428 ,  H05K3/467 ,  H05K2201/0179 ,  H01L2924/00

Abstract: Die Erfindung beschreibt einen Bauteil ausgerüstet mit Dünnschichtschaltkreis. Zur Realisierung des Bauteils mit Dünnschichtschaltkreis werden auf einem Substrat (1) aus einem isolierenden Material neben den Streifenleitungen Kondensatoren oder Kondensatoren und Widerstände oder Kondensatoren, Widerstände und Induktoren mittels Dünnschichttechniken schon direkt auf das Substrat aufgebracht. Durch die teilweise oder vollständige Integration von passiven Bauelementen wird ein Bauteil mit geringem Raumbedarf geschaffen.

Abstract translation: 本发明描述了配备有薄膜电路的装置。 对于具有薄膜电路装置的实现在基板上（1）由相邻的带状线电容或电容器和电阻器，或电容器，电阻器和电感器通过已经直接施加到基底上的薄膜的技术的绝缘材料制成。 由于无源组件的部分或全部一体化，一个组件设置有一个小的空间需求。

公开(公告)号：EP1093328A2

公开(公告)日：2001-04-18

申请号：EP00308916.6

申请日：2000-10-10

Applicant: ROHM AND HAAS COMPANY

Inventor： Nacker, Wayne E. ,  Carpenter, Richard W.

IPC: H05K3/02 ,  H05K1/16 ,  H01L21/48

CPC classification number: H05K1/167 ,  H01L21/4846 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/027 ,  H05K3/20 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0338

Abstract: To form thin film electrical components, a thin film having desired electrical properties is deposited on a substrate of dissimilar material. Thermal energy from a computer guided laser is used to remove selected portions of the thin film.
In accordance with one aspect of the invention, the thin film is an electrically conducting material, such as platinum or doped platinum, and the substrate is metal foil, such as copper foil. The thermal energy from the laser ablates away portions of the thin film.
In accordance with another aspect of the invention, a layer of zero valence metal is deposited on a dielectric material substrate which has a melting point or decomposition temperature substantially above that of the zero valence metal. The zero valence metal layer is patterned to form electronic circuitry components by computer guided laser which provides sufficient thermal energy to boil away selected portions of the zero valence metal layer.
In one preferred embodiment, electronic circuitry is formed from a three-layer composite comprising nickel foil; a dielectric material, such as silica deposited on the foil; and a zinc layer deposited on the dielectric material. The zinc layer, having a boiling point substantially below the melting points of the dielectric material and the nickel foil, is patterned by laser-derived thermal energy.

Abstract translation: 为了形成薄膜电气部件，将具有期望的电性能的薄膜沉积在不同材料的基板上。 使用来自计算机引导激光的热能来去除所选择的薄膜部分。 根据本发明的一个方面，薄膜是诸如铂或掺杂铂的导电材料，并且衬底是诸如铜箔的金属箔。 来自激光器的热能消除了薄膜的部分。 根据本发明的另一方面，一种零价金属层沉积在电介质材料基片上，其熔点或分解温度基本上高于零价金属的熔点或分解温度。 将零价金属层图案化以通过计算机引导激光器形成电子电路部件，该激光器提供足够的热能来去除零价金属层的选定部分。 在一个优选实施例中，电子电路由包括镍箔的三层复合材料形成; 介电材料，例如沉积在箔上的二氧化硅; 以及沉积在电介质材料上的锌层。 具有基本上低于介电材料和镍箔的熔点的沸点的锌层通过激光衍生的热能来图案化。

公开(公告)号：EP0836229A3

公开(公告)日：1999-06-02

申请号：EP97305828.2

申请日：1997-08-01

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Saia, Richard Joseph ,  Durocher, Kevin Matthew ,  Cole, Herbert Stanley

IPC: H01L23/538 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/19 ,  H01L24/82 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/162 ,  H05K1/167 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/0361 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer (16,18) over one or both surfaces of a dielectric film (10); applying a metallization layer (22) over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer (24a) over the metallization layer; and applying a capacitor electrode layer (26a) over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor (28); and the metallization layer and the resistor layer are patterned to form an inductor (33) and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

公开(公告)号：EP0451500B1

公开(公告)日：1997-11-19

申请号：EP91103285.2

申请日：1991-03-05

Applicant: International Business Machines Corporation

Inventor： Lauffer, John Matthew ,  Schumacher, Richard Anthony

IPC: H05K3/46 ,  H01L23/538 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  Y10S257/916 ,  Y10T29/435