摘要:
A mounting method of mounting chips on a substrate includes a temporarily-bonding process of temporarily individually bonding the chips on the substrate, and a main-bonding process of firmly individually bonding, on the substrate, the chips temporarily bonded on the substrate. The temporarily-bonding process is to perform a first basic process, repeatedly depending on the number of the chips to be mounted on the substrate. The first basic process includes a first step and a second step. The first step is to align, on a first metal layer of the substrate, a second metal layer of each chip. The second step is to temporarily bond each chip by subjecting the first and second metal layers to solid phase diffusion bonding. The main-bonding process is to perform a second basic process, repeatedly depending on the number of the chips on the substrate. The second basic process includes a third step and a fourth step. The third step is to recognize a position of each chip temporarily mounted on the substrate. The fourth step is to firmly bond each chip by subjecting the first and second metal layers to liquid phase diffusion bonding.
摘要:
According to one embodiment, a semiconductor device (110) includes a semiconductor element (20), a mounting member (70) including Cu, and a bonding layer (50) provided between the semiconductor element (20) and the mounting member (70). The bonding layer (50) includes a first region (R1) including Ti and Cu, and a second region (R2) provided between the first region (R1) and the mounting member (70), and including Sn and Cu. A first position (P1) along the first direction is positioned between the semiconductor element (20) and a second position (P2) along the first direction. The first position (P1) is where the composition ratio (51r) of Ti in the first region (R1) is 0.1 times a maximum value (51x) of the composition ratio (51r) of Ti. The second position (P2) is where the composition ratio (52r) of Sn in the second region (R2) is 0.1 times a maximum value (52x) of the composition ratio (52r) of Sn. A distance (L1) between the first position (P1) and the second position (P2) is not less than 0.1 micrometres. According to another embodiment, a semiconductor device (120) includes a semiconductor element (20), a mounting member (70) including Cu, a first layer (41) provided between the semiconductor element (20) and the mounting member (70), the first layer (41) including Ti, a second layer (42) provided between the first layer (41) and the mounting member (70), the second layer (42) including Sn and Cu and a third layer (43) provided between the first layer (41) and the second layer (42), the third layer (43) including at least one selected from Ni, Pt, and Pd. In both embodiments, the semiconductor device (110, 120) is formed by bonding the semiconductor element (20) to the mounting member (70) by solid solution bonding. Thereby, a semiconductor device (110, 120) having good heat dissipation and high productivity can be provided.
摘要:
The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30') is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30') has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30') is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component (10).
摘要:
A method for bonding an electronics chip (10) to a substrate (12), the method comprising the steps of: coating a bonding area (14) of the chip (10) with a first metal layer (18); providing a bonding area (24) of the substrate (12) and/or the bonding area (14) of the chip (10) with a low melting point metal layer (30), wherein the bonding area (24) of the substrate (12) comprises a second metal layer (28); attaching a spacer (20) to the chip (10) and/or the substrate (12); positioning and fixing the chip (10) on the substrate (12); and transient liquid phase bonding the chip (10) to the substrate (12) by melting the low melting point layer (30), wherein the spacer (20) provides a specific distance between the first metal layer (18) and the second metal layer (28).
摘要:
A metal inter-diffusion bonding method comprises providing a stack of a first metal on a surface of both a first wafer and second wafer to be joined together. Said first metal is susceptible to oxidation in air. A layer of a second metal is provided on the first metal and has a melting point lower than that of the first metal. On the top surface of each stack of first metal is the layer of second metal sufficiently thick to both inhibit oxidation of the top surface of the first metal and to ensure that unreacted Sn remains when partners are brought together. A bond is initiated between the first and second wafers by bringing the layers of the second metal on each wafer into contact at a bonding temperature that is below the melting point of the second metal, by applying a bonding force that is sufficient to initiate inter-diffusion at an interface between the layers of the second metal. The bonding temperature is increased whilst applying the bonding force to achieve a desired inter-diffusion at the bond interface, thereby bonding the first and second wafers together, and no pre-treatment of the wafers is required prior to bonding.
摘要:
A method for bonding nano-elements to a surface is described. The method includes applying a layer of a first metal to a first end of a plurality of substantially aligned nano-elements, positioning a layer of a second metal adjacent to the layer of the first metal, placing a compressive force across the nano-elements, the metal layers, and the substrate, and elevating the temperature of the nano-elements, the metal layers, and a substrate adjacent the layer of the second metal such that the metal layers form at least one of a eutectic bond, a metal solid solution, and an alloy bond between the nano-elements and the substrate.
摘要:
Es wird ein Metallschichtsystem zur Verlötung von Leistungshalbleitern mit Kühlkörpern vorgestellt, bei dem gegenüber den bekannten vier Metallschichtsystemen auf zwei Metallschichten verzichtet werden kann. Dabei wird auf die Halbleiterkörperrückseite (3) eine Chromschicht (4) aufgesputtert und auf die Chromschicht (4) eine Zinnschicht (5) aufgedampft. Danach wird der Halbleiterkörper (1) mit der metallenen Trägerplatte (2) durch Erwärmen auf Temperaturen oberhalb 250°C unmittelbar, d.h. ohne weitere Zusätze, verlötet.