公开(公告)号：EP0852395A3

公开(公告)日：1998-07-15

申请号：EP97122631.1

申请日：1997-12-22

Applicant: MOTOROLA, INC.

Inventor： Greer, Stuart E. ,  Clegg, David ,  Burnette, Terry Edward

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L2224/11003 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K3/3478 ,  H05K2201/035 ,  H05K2201/10674 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/041 ,  H01L2924/00

Abstract: Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process. The method includes the steps of providing a semiconductor device having at least one first interconnect structure connected to a surface of the semiconductor device (501), and a substrate having a plurality of metallized pads (503); placing an at least one second interconnect structure in aligned contact with one or more of the plurality of metallized pads (505); placing the at least one first interconnect structure in aligned contact with one or more of the plurality of metallized pads (507); and simultaneously reflowing the at least one first interconnect structure and the at least one second interconnect structure such that the semiconductor device and at least one second interconnect structure are connected to the metallized pads of the substrate (509).

Abstract translation: 将焊料凸块多路连接到用于组装集成电路封装的各种基板包括将具有焊料凸块结构（314）的半导体基板（312）放置成与具有芯片焊盘（322,334）的陶瓷基板（320）接触，并将该 结构与球栅阵列球体（352）接触以便在单个流动过程中形成CBGA（360），该方法包括以下步骤：提供具有至少一个连接到半导体表面的第一互连结构的半导体器件 装置（501）和具有多个金属化焊盘（503）的衬底;将至少一个第二互连结构放置成与所述多个金属化焊盘（505）中的一个或多个对准接触;将所述至少一个第一互连 结构与所述多个金属化焊盘（507）中的一个或多个对准接触;以及同时回流所述至少一个第一互连结构和所述至少一个第二互连 使得半导体器件和至少一个第二互连结构连接到衬底（509）的金属化焊盘。

公开(公告)号：EP0815591A2

公开(公告)日：1998-01-07

申请号：EP96923183.0

申请日：1996-02-06

Applicant: GRUMMAN AEROSPACE CORPORATION

Inventor： KOH, Wei, H. ,  McCAUSLAND, Connie, S.

IPC: H05K1 ,  H01L21 ,  H01L23 ,  H05K3

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/0094 ,  H05K3/4061 ,  H05K2201/035 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09981 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method for forming a conductive vias in a non-conductive substrate having a through-hole formed therein intermediate two side thereof. The method utilizes the steps of: applying gold paste to the through-hole so as to provide electrical conduction therethrough; and under firing the gold paste when a thin conductive film is present upon the substrate and fully firing the gold paste when no thin conductive film is present on the substrate. Under firing the gold paste when a thin-film is present upon the substrate prevents degradation of the thin conductive film. Subsequent processing of the gold paste assures the integrity and reliability thereof. Thus, the gold paste provides enhanced conductivity and improved reliability, as compared to contemporary thin-film vias.

公开(公告)号：EP0790644A2

公开(公告)日：1997-08-20

申请号：EP97101426.1

申请日：1997-01-30

Applicant: AB Mikroelektronik Gesellschaft m.b.H.

Inventor： Wilczek, Klaus-Peter

IPC: H01L21/70 ,  H01L27/01 ,  H01C17/28

CPC classification number: H05K1/167 ,  H01C17/283 ,  H05K1/092 ,  H05K3/1291 ,  H05K3/248 ,  H05K2201/035 ,  H05K2203/086 ,  H05K2203/1126

Abstract: Verfahren zum Herstellen elektrischer Schaltkreise, welche durch Edelmetalle kontaktierte und über Leiterbahnen aus Kupfer elektrisch verbundene Widerstände und gegebenenfalls Dielektrika umfassen, wobei zumindest die Kontakte der Widerstände aus Edelmetall und die anschließenden Leiterbahnen aus Kupfer durch Aufbringen von Pasten und deren Sintern erzeugt werden. Das Sintern der Leiterbahnen aus Kupfer bei Temperaturen erfolgt oberhalb von 850°C unter Stickstoffatmosphäre erfolgt, wobei eine elektrisch leitende Trennschicht (5) zwischen Edelmetallkontakten und Leiterbahn die Bildung eines Eutektikums Edelmetall/Kupfer verhindert.

Abstract translation: 通过糊料施加和烧结制造贵金属和铜的相邻电路线的电阻器触点，至少在铜电路线的烧结在氮气氛下在850℃以上进行，并且在触点之间设置导电分离层 和电路线，以防止贵金属/铜共晶形成。 分离层通过在设置铜电路线之前施加粘合膏（主要是镍），或者通过用导电粘合剂例如在烧结之后密封接触和电路线之间留下的间隙来形成。 的银分散在聚酰亚胺中。

公开(公告)号：EP0745315A1

公开(公告)日：1996-12-04

申请号：EP95944372.0

申请日：1995-12-19

Applicant: MOTOROLA, INC.

Inventor： BRADLEY, Edwin, L., III ,  BANERJI, Kingshuk ,  KAZEM-GOUDARZI, Vahid

IPC: B23K35 ,  H05K3

CPC classification number: H05K3/3463 ,  B23K35/025 ,  B23K35/26 ,  B23K2201/04 ,  B23K2201/12 ,  H05K3/1216 ,  H05K3/3484 ,  H05K2201/035 ,  H05K2201/10992 ,  H05K2203/043

Abstract: A soldering process uses two or more different solder alloys. A first solder alloy (115) that undergoes a solid-to-liquid transition at a first temperature is coated (20) onto the solderable surfaces (105) of a printed circuit board (100). A solder paste (120) that undergoes this solid-to-liquid transition at a temperature greater than the first temperature is deposited on the coated solderable portions, and is heated to a temperature that is above the first temperature but below the second temperature. During this time, the first solder alloy liquifies, while the solder paste does not. The first solder alloy wets to the individual particles in the solder paste, and alloys to the solderable surfaces and the solder particles in the solder paste. The soldering composition is subsequently cooled (40) to solidify the first solder material, forming a solid and substantially planar coating on the solderable portions of the printed circuit board.

公开(公告)号：EP0660651A1

公开(公告)日：1995-06-28

申请号：EP94120404.2

申请日：1994-12-22

Applicant: SUMITOMO METAL CERAMICS INC. ,  NIPPONDENSO CO., LTD.

Inventor： Tanifuji, Nozomi ,  Naito, Akihiko ,  Sawada,Koji ,  Nomura,Tohru ,  Miyase,Yoshiyuki ,  Nagasaka,Takashi

IPC: H05K3/46 ,  H01L23/538 ,  H05K1/00

CPC classification number: H05K3/248 ,  H01L23/49883 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/113 ,  H05K3/245 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/035 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A multilayer ceramic circuit substrate having therein internal conductor patterns (2) comprising W and/or Mo as a main component and surface conductor patterns (5) comprising Cu as a main component formed onto a surface layer of the multilayer ceramic circuit substrate, wherein an intermediate metal layer (4) comprising 40 to 90 wt.% of W and/or Mo and 10 to 60 wt.% of at least one element selected from the group consisting of Ir, Pt, Ti, and Cr is formed in through-holes (3) of the surface layer and on parts of the surface layer in the vicinity of the through holes (3) on the surface layer, whereby the internal conductor patterns (2) and the surface conductor patterns (5) are electrically connected through the intermediate metal layer (4). The alumina multilayer ceramic circuit substrate provides an excellent bonding strength and electrical conductivity between the internal conductors and the surface conductors and enables high precision wiring and miniaturization of an electronic circuit part.

Abstract translation: 其中具有内部导体图案（2），包括W和/或Mo作为主要成分和表面导体图案（5）包括Cu作为形成到多层陶瓷电路基板的一个表面层的主要成分，worin的多层陶瓷电路基板 在形成由W和/或Mo的40〜90％（重量）和选自铱，铂，钛，和Cr中选出的至少一种元素的10〜60％（重量）中间金属层（4）通过 孔（3）的表面层的与上贯通孔的附近的表面层的部分（3）的表面层，由此，内部导体图案（2）和所述表面导体图案（5）电通过连接上 中间金属层（4）。 氧化铝陶瓷多层电路衬底提供内部导体和表面导体之间的优异的粘接强度和导电性，并使电子电路部的高精度的布线和小型化。

公开(公告)号：EP0609861A2

公开(公告)日：1994-08-10

申请号：EP94101559.6

申请日：1994-02-02

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Nakamura, Yoshifumi ,  Bessho, Yoshihiro ,  Yuhaku, Satoru ,  Hakotani, Yasuhiko ,  Itagaki, Minehiro ,  Miura, Kazuhiro

IPC: H01L21/48

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/4867 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/035 ,  H05K2201/0367 ,  Y10T29/49163 ,  Y10T428/24273 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00014

Abstract: The method of manufacturing a ceramic substrate having a plurality of bumps of the present invention, includes the steps of: forming a bump forming layer having a plurality of holes therein on at least one of upper and lower faces of a laminated body of green sheets; filling the holes in the bump forming layer with a bump forming paste; sintering the laminated body of the green sheets and the bump forming layer; and forming bumps made of the sintered bump forming paste by removing the bump forming layer.

Abstract translation: 本发明的具有多个凸块的陶瓷基板的制造方法包括以下步骤：在生片层叠体的上下表面的至少一个上形成具有多个孔的凸块形成层; 用凸块形成膏填充凸块形成层中的孔; 烧结生片和凸起形成层的层叠体; 以及通过去除所述凸块形成层来形成由所述烧结凸块形成用糊料形成的凸块。

公开(公告)号：EP0245770B1

公开(公告)日：1993-03-17

申请号：EP87106589.2

申请日：1987-05-07

Applicant: SUMITOMO METAL CERAMICS INC.

Inventor： Nishigaki, Susumu ,  Fukuda, Junzo Arimatsu Green Heights 14-11 ,  Kawabe, Hiroshi Corpo Tokai 101 ,  Yano,Shinsuke

IPC: H05K1/03 ,  H05K3/46 ,  H05K1/05

CPC classification number: H05K3/4061 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/167 ,  H05K3/181 ,  H05K3/246 ,  H05K3/248 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/0352 ,  Y10S428/901 ,  Y10T428/12507 ,  Y10T428/12514 ,  Y10T428/12896 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

公开(公告)号：EP0245770A3

公开(公告)日：1989-03-15

申请号：EP87106589.2

申请日：1987-05-07

Applicant: SUMITOMO METAL CERAMICS INC.

Inventor： Nishigaki, Susumu ,  Fukuda, Junzo Arimatsu Green Heights 14-11 ,  Kawabe, Hiroshi Corpo Tokai 101 ,  Yano,Shinsuke

IPC: H05K1/03 ,  H05K3/46 ,  H05K1/05

CPC classification number: H05K3/4061 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/167 ,  H05K3/181 ,  H05K3/246 ,  H05K3/248 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/0352 ,  Y10S428/901 ,  Y10T428/12507 ,  Y10T428/12514 ,  Y10T428/12896 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer ceramic substrate with multilayered circuit patterns, the improvement in which internal conductors for wiring are formed by a Ag base conductive materials capable of being co-fired with multilayered green ceramic substrate sheets in an oxidizing atmosphere and external conductors electrically connected with the internal conductors are formed by a Cu base conductive material, the external Cu conductors being formed in such a manner so that a liquid phase of Cu-Ag is not formed at the interface of the Cu conductor and the Ag conductor. Further high reliable resistors of RuO₂ or Bi₂Ru₂O₇ type may be integrally formed onto and/or inside the substrate. In such an arrangement, problems or difficulties caused due to Ag migration, incomplete binder removal, solder leaching, etc., are eliminated and thereby there can be a multilayer substrate wit a high reliability and a high pattern precision.

公开(公告)号：EP0259035A3

公开(公告)日：1989-01-25

申请号：EP87307154.2

申请日：1987-08-13

Applicant: STC PLC

Inventor： Gainey, Trevor Clifford ,  Hall, Ian ,  Jones, Alan Robert

IPC: H01L21/60 ,  H01L21/58

CPC classification number: H01L24/81 ,  H01L24/31 ,  H01L24/83 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/15787 ,  H05K1/092 ,  H05K1/111 ,  H05K3/248 ,  H05K3/341 ,  H05K2201/035 ,  H05K2201/0373 ,  H05K2201/10166 ,  H05K2201/10969 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A power component such as a power transistor is mounted on an insulating substrate of e.g. Beryllia. By using a thick film deposition technique. A first layer (2) is deposited and a second layer (3) is deposited over the first layer to produce a regular series of troughs and lans, in the preferred embodiment troughs and ridges, whereby voiding in the solder bond is minimised if not eliminated to thus maintain a good thermal conductivity between the component and the substrate.

公开(公告)号：EP0248566A2

公开(公告)日：1987-12-09

申请号：EP87304510.8

申请日：1987-05-21

Applicant: AT&T Corp.

Inventor： LoVasco, Francis ,  Oien, Michael Ackman

IPC: H01L21/58 ,  H01L21/60 ,  H05K3/34

CPC classification number: H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/81024 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/035 ,  H05K2201/0379 ,  H05K2201/09909 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/043 ,  H05K2203/0465 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/29099

Abstract: A solder joint assembly technique applies controlled volumes of solder to pads of both package and substrate (31, 32). The two units are positioned adjacent each other with the pads and solder deposits mechanically maintained in registration with each other (34, 35). The assembly is reflowed and the final separation between package and substrate at which the resulting solder joint solidifies is mechanically controlled in order to control a geometry of the resultant solidified joint (36, 37). The solder volume deposits may assume various forms including spherical bumps and solder paste deposits.

Abstract translation: 焊料接头组件技术适用焊料的受控体积为两者封装的焊盘和基片（31，32）。 这两个单元被定位成机械性地保持在登记海誓山盟（34，35）的焊盘和焊料沉积相邻海誓山盟。 该组件被软熔和封装基板之间和将所得的焊点固化是为了控制所得的几何机械控制的最终分离凝固接头（36，37）。 焊料体积沉积物可以采取各种形式，包括球形凸块和焊锡膏沉积。