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    POWER OVERLAY STRUCTURE FOR A MULTI-CHIP SEMICONDUCTOR PACKAGE
    3.
    发明公开
    POWER OVERLAY STRUCTURE FOR A MULTI-CHIP SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：EP4510185A1

    公开(公告)日：2025-02-19

    申请号：EP24193418.1

    申请日：2024-08-07

    Applicant: General Electric Company

    Inventor： STEVANOVIC, Ljubisa ,  GOWDA, Arun Virupaksha ,  KAPUSTA, Christopher James ,  TUOMINEN, Risto Ilkka Sakari

    IPC: H01L23/64

    Abstract: A multi-chip semiconductor package (200) includes a dielectric interconnect layer (260) having an upper surface (261) and a bottom surface, at least one common source pad (280) disposed on the upper surface of the interconnect layer, at least one common gate pad (292) disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices (100) each including a gate pad and at least one source pad adhered onto the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel with one another, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.

    ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME
    5.
    发明公开
    ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME 审中-公开
    通过图案预定义的电子封装及其制造和使用方法

    公开(公告)号：EP3038145A3

    公开(公告)日：2016-07-06

    申请号：EP15198634.6

    申请日：2015-12-09

    Applicant: General Electric Company

    Inventor： GOWDA, Arun Virupaksha ,  MCCONNELEE, Paul Alan ,  TUOMINEN, Risto llkka

    IPC: H01L21/60 ,  H01L21/66 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L22/12 ,  H01L22/14 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/19105 ,  H01L2924/37001

    Abstract: An electronic package is provided. The electronic package includes a substrate (102) and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer (120) disposed on portions of the substrate (102) to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer (152) disposed on at least a portion of the metal built-up layer (120). Moreover, the electronic package includes a second conductive layer (160) disposed on the first conductive layer (152), where the plurality of vias is disposed at least in part in the metal built-up layer (120), the first conductive layer (152), and the second conductive layer (160).

    Abstract translation: 提供电子套餐。 电子封装包括衬底（102）和由对应的多个预定义的通孔图案限定的多个通孔。 所述电子封装还包括设置在所述衬底（102）的部分上的金属构建层（120），以提供所述多个通孔的多个预定义通孔位置和所述多个预定义通孔图案。 而且，电子封装包括设置在金属组合层（120）的至少一部分上的第一导电层（152）。 此外，电子封装件包括设置在第一导电层（152）上的第二导电层（160），其中多个通孔至少部分地设置在金属组合层（120）中，第一导电层 152）和第二导电层（160）。

    ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME
    7.
    发明公开
    ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME 审中-公开
    另外，制造及其用途定的模式和方法，电子PACKS

    公开(公告)号：EP3038145A2

    公开(公告)日：2016-06-29

    申请号：EP15198634.6

    申请日：2015-12-09

    Applicant: General Electric Company

    Inventor： GOWDA, Arun Virupaksha ,  MCCONNELEE, Paul Alan ,  TUOMINEN, Risto llkka

    IPC: H01L21/60 ,  H01L21/66 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L22/12 ,  H01L22/14 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/19105 ,  H01L2924/37001

    Abstract: An electronic package is provided. The electronic package includes a substrate (102) and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer (120) disposed on portions of the substrate (102) to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer (152) disposed on at least a portion of the metal built-up layer (120). Moreover, the electronic package includes a second conductive layer (160) disposed on the first conductive layer (152), where the plurality of vias is disposed at least in part in the metal built-up layer (120), the first conductive layer (152), and the second conductive layer (160).

    Abstract translation: 提供了一种电子封装。 通过图案的电子封装包括衬底（102）和通过相应的多个限定通孔的多个预先定义的。 电子封装进一步设置在基底（102）的部分的金属堆焊层（120），以提供通孔位置的预先定义的多个部分并加以经由通孔的多个图案中的预定义的多元性。 所以，电子封装包括设置在金属堆焊层（120）的至少一部分的第一导电层（152）。 更上方，电子封装件包括设置在第一导电层（152），其中，通孔的数目为至少在金属堆焊层（120）设置在部分上的第二导电层（160），第一导电层（ 152），和第二导电层（160）。

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