公开(公告)号：US08900913B2

公开(公告)日：2014-12-02

申请号：US13588898

申请日：2012-08-17

Applicant: Chuan-Jin Shiu ,  Po-Shen Lin ,  Shen-Yuan Mao ,  Cheng-Chi Peng

Inventor： Chuan-Jin Shiu ,  Po-Shen Lin ,  Shen-Yuan Mao ,  Cheng-Chi Peng

IPC: H01L33/00 ,  H01L21/00 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L2224/13 ,  H01L2933/0025

Abstract: An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least one optoelectronic device is formed in the substrate; forming an insulating layer on the substrate; forming a conducting layer on the insulating layer on the substrate, wherein the conducting layer is electrically connected to the at least one optoelectronic device; and spraying a solution of light shielding material on the second surface of the substrate to form a light shielding layer on the second surface of the substrate.

Abstract translation: 本发明的一个实施例提供了一种用于形成芯片封装的方法，其包括：提供具有第一表面和第二表面的衬底，其中在衬底中形成至少一个光电器件; 在所述基板上形成绝缘层; 在所述基板上的所述绝缘层上形成导电层，其中所述导电层电连接到所述至少一个光电器件; 以及在所述基板的第二表面上喷射遮光材料的溶液，以在所述基板的第二表面上形成遮光层。

公开(公告)号：US08785956B2

公开(公告)日：2014-07-22

申请号：US13560842

申请日：2012-07-27

Applicant: Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang ,  Hui-Ching Yang ,  Chiung-Lin Lai

Inventor： Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang ,  Hui-Ching Yang ,  Chiung-Lin Lai

IPC: H01L33/00 ,  H01L21/00 ,  H01L33/52 ,  H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14623 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L33/52 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 形成在所述基板中的光电子器件; 设置在所述基板上的导电层，其中所述导电层电连接到所述光电子器件; 设置在所述基板和所述导电层之间的绝缘层; 设置在所述基板的第二表面上的第一遮光层; 以及第二遮光层，其设置在所述第一遮光层上并与所述第一遮光层直接接触，其中所述第一遮光层和所述第二遮光层之间的接触界面。

公开(公告)号：US08633558B2

公开(公告)日：2014-01-21

申请号：US12981640

申请日：2010-12-30

Applicant: Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

Inventor： Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

IPC: H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.

Abstract translation: 该实施例提供了用于芯片的封装结构及其制造方法。 用于芯片的封装结构包括具有衬底和焊盘结构的芯片。 该芯片具有上表面和下表面。 上包装层覆盖芯片的上表面。 间隔层位于上包装层和芯片之间。 导电路径电连接到接合焊盘结构。 防反射层设置在间隔层和上包装层之间。 重叠区域在抗反射层和间隔层之间。

公开(公告)号：US08536671B2

公开(公告)日：2013-09-17

申请号：US13154337

申请日：2011-06-06

Applicant: Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

Inventor： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC: H01L31/0203

CPC classification number: H01L27/14623 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L33/44 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having a first surface and a second surface; an optical device between the first surface and the second surface of the substrate; a protection layer formed on the second surface of the substrate, wherein the protection layer has at least an opening; at least a conducting bump formed in the opening of the protection layer and electrically connected to the optical device; and a light shielding layer formed on the protection layer, wherein the light shielding layer is further extended onto a sidewall of the opening of the protection layer.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 在所述基板的所述第一表面和所述第二表面之间的光学装置; 形成在所述基板的第二表面上的保护层，其中所述保护层具有至少一个开口; 至少形成在所述保护层的开口中并电连接到所述光学装置的导电凸起; 以及形成在所述保护层上的遮光层，其中所述遮光层进一步延伸到所述保护层的开口的侧壁上。

公开(公告)号：US20110291139A1

公开(公告)日：2011-12-01

申请号：US13114750

申请日：2011-05-24

Applicant: Hsin-Chih CHIU ,  Chia-Ming Cheng ,  Chuan-Jin SHIU ,  Bai-Yao LOU

Inventor： Hsin-Chih CHIU ,  Chia-Ming Cheng ,  Chuan-Jin SHIU ,  Bai-Yao LOU

IPC: H01L33/48 ,  H01L31/18 ,  H01L31/02

CPC classification number: H01L27/14618 ,  H01L31/048 ,  H01L2224/13 ,  H01L2933/0066 ,  Y02E10/50

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optical device disposed on the first surface; a conducting pad disposed on the first surface; a first alignment mark formed on the first surface; and a light shielding layer disposed on the second surface and having a second alignment mark, wherein the second alignment mark corresponds to the first alignment mark.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在所述第一表面上的光学装置; 设置在所述第一表面上的导电垫; 形成在第一表面上的第一对准标记; 以及遮光层，其设置在所述第二表面上并且具有第二对准标记，其中所述第二对准标记对应于所述第一对准标记。

公开(公告)号：US08890191B2

公开(公告)日：2014-11-18

申请号：US13536628

申请日：2012-06-28

Applicant: Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang

Inventor： Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang

IPC: H01L33/00 ,  H01L21/00 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/1463 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 形成在所述基板中的光电子器件; 设置在所述基板上的导电层，其中所述导电层电连接到所述光电子器件; 设置在所述基板和所述导电层之间的绝缘层; 遮光层，其设置在所述基板的所述第二表面上并与所述导电层直接接触，其中所述遮光层具有大于约80％的遮光率并且具有暴露所述导电层的至少一个开口; 以及布置在所述遮光层的开口中以与所述导电层电接触的导电凸块，其中所述遮光层和所述导电凸起部分都基本上完全覆盖所述基板的第二表面。

公开(公告)号：US08604578B2

公开(公告)日：2013-12-10

申请号：US13279183

申请日：2011-10-21

Applicant: Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

Inventor： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

IPC: H01L31/0203

CPC classification number: H01L27/14623 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/552 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/10126 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer located on the second surface of the substrate, wherein the protection layer has an opening; a light shielding layer located on the second surface of the substrate, wherein a portion of the light shielding layer extends into the opening of the protection layer; a conducting bump disposed on the second surface of the substrate and filled in the opening of the protection layer; and a conducting layer located between the substrate and the protection layer, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 位于所述基板的第二表面上的保护层，其中所述保护层具有开口; 位于所述基板的第二表面上的遮光层，其中所述遮光层的一部分延伸到所述保护层的开口中; 设置在所述基板的第二表面上并填充在所述保护层的开口中的导电凸块; 以及位于所述衬底和所述保护层之间的导电层，其中所述导电层将所述光电器件电连接到所述导电凸块。

公开(公告)号：US20110156074A1

公开(公告)日：2011-06-30

申请号：US12981600

申请日：2010-12-30

Applicant: Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

Inventor： Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC: H01L33/60 ,  H01L33/48

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

Abstract translation: 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

公开(公告)号：US08836134B2

公开(公告)日：2014-09-16

申请号：US13738082

申请日：2013-01-10

Applicant: Po-Shen Lin ,  Chuan-Jin Shiu ,  Bing-Siang Chen ,  Chen-Han Chiang ,  Chien-Hui Chen ,  Hsi-Chien Lin ,  Yen-Shih Ho

Inventor： Po-Shen Lin ,  Chuan-Jin Shiu ,  Bing-Siang Chen ,  Chen-Han Chiang ,  Chien-Hui Chen ,  Hsi-Chien Lin ,  Yen-Shih Ho

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L21/78 ,  B81C1/00888 ,  H01L21/561 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.

Abstract translation: 提供一种制造半导体堆叠封装的方法。 在晶片和基板上进行单晶化处理，晶片和晶片被堆叠在其上。 去除切割区域上的晶片的一部分，以在晶片的芯片的边缘上形成应力集中区域。 然后切割晶片和基板，并且迫使应力集中在晶片的芯片的边缘上。 结果，芯片的边缘变形。 因此，防止了应力延伸到芯片的内部。 还提供半导体堆叠封装。

公开(公告)号：US08575634B2

公开(公告)日：2013-11-05

申请号：US12981600

申请日：2010-12-30

Applicant: Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

Inventor： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC: H01L33/60 ,  H01L33/48

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

Abstract translation: 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。