公开(公告)号：US09698123B2

公开(公告)日：2017-07-04

申请号：US13235166

申请日：2011-09-16

申请人： Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

发明人： Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

IPC分类号： H01L25/065 ,  H01L23/00 ,  H05K3/46 ,  H05K1/14

CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H05K1/141 ,  H05K3/4697 ,  H05K2201/1053 ,  H01L2924/014 ,  H01L2924/00

摘要： An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

公开(公告)号：US06693342B2

公开(公告)日：2004-02-17

申请号：US09846057

申请日：2001-04-30

申请人： Charles E. Larson ,  Timothy E. Murphy ,  Bryan L. Taylor ,  Jon M. Long ,  Mark W. Ellis ,  Vincent L. Riley

发明人： Charles E. Larson ,  Timothy E. Murphy ,  Bryan L. Taylor ,  Jon M. Long ,  Mark W. Ellis ,  Vincent L. Riley

IPC分类号： H01L2900

CPC分类号： H01L21/6835 ,  H01L21/67092 ,  H01L21/6838 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2924/0002 ,  Y10S438/94 ,  Y10S438/977 ,  H01L2924/00

摘要： A microelectronic substrate and method for manufacture. In one embodiment, the microelectronic substrate includes a body having a first surface, a second surface facing a direction opposite from the first surface, and a plurality of voids in the body between the first and second surfaces. The voids can extend from the first surface to a separation region beneath the first surface. At least one operable microelectronic device is formed at and/or proximate to the first surface of the substrate material, and then a first stratum of the microelectronic substrate above the separation region is separated from a second stratum of the microelectronic substrate below the separation region. The first stratum of the microelectronic substrate can be further separated into discrete microelectronic dies before the first stratum is separated from the second stratum. In one aspect of this embodiment, the substrate can support a film and microelectronic devices can be formed in the film and/or in the substrate.

摘要翻译： 微电子基板及其制造方法。 在一个实施例中，微电子衬底包括具有第一表面，面向与第一表面相反的方向的第二表面的本体和在第一表面和第二表面之间的主体中的多个空隙。 空隙可以从第一表面延伸到第一表面下方的分离区域。 至少一个可操作的微电子器件形成在衬底材料的第一表面处和/或靠近衬底材料的第一表面处，然后在分离区域上方的微电子衬底的第一层与分离区域下方的微电子衬底的第二层分离。 在第一层与第二层分离之前，微电子衬底的第一层可以进一步分离成离散的微电子管芯。 在该实施例的一个方面中，衬底可以支撑膜，并且可以在膜和/或衬底中形成微电子器件。

公开(公告)号：US5210375A

公开(公告)日：1993-05-11

申请号：US723136

申请日：1991-06-28

申请人： Jon M. Long

发明人： Jon M. Long

IPC分类号： H01L21/68 ,  H01L23/00 ,  H01L23/495 ,  H05K3/34

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/49555 ,  H01L23/562 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2201/10424 ,  H05K2201/10689 ,  Y02P70/613 ,  Y10T29/49121

摘要： The exposed portions of the leads of a semiconductor chip package are first bent in a forming process so that the ends of the leads are in proper positions to be attached to and electrically connected to contacts on a printed circuit board. Intermediate portions of the leads between the distal ends and the package body for connection to the printed circuit board and the package body are enclosed and fixed in position by a carrier body to hold the leads in position and to reduce the effects of any bending in destroying the coplanarity of the distal lead ends of the package. The package with the carrier body may be mounted onto the printed circuit board without first removing the carrier body. After the distal ends of the leads have been soldered to the printed circuit board, the carrier body is then removed.

摘要翻译： 半导体芯片封装的引线的暴露部分首先在成形工艺中弯曲，使得引线的端部处于适当位置，以附着到电连接到印刷电路板上的触点。 用于连接到印刷电路板和封装体的远端和封装主体之间的引线的中间部分由载体主体封闭并固定在适当的位置，以将引线保持在适当位置并减少任何弯曲的破坏的影响 包装的远端引线端的共面性。 具有承载体的包装可以安装在印刷电路板上，而无需首先移除载体主体。 在将引线的末端焊接到印刷电路板之后，然后移除载体主体。

公开(公告)号：US20130071969A1

公开(公告)日：2013-03-21

申请号：US13607481

申请日：2012-09-07

申请人： Nagesh Vodrahalli ,  Jon M. Long

发明人： Nagesh Vodrahalli ,  Jon M. Long

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/11474 ,  H01L2224/11845 ,  H01L2224/11906 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/1703 ,  H01L2224/29099 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014

摘要： A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.

摘要翻译： 制造电子组件的方法包括制造第一和第二互连。 第一互连适于将第一裸片与衬底相互连接。 第二互连适于将第一管芯与第二管芯相互连接。 该方法还包括将第一模具，第二模具和衬底组装在一起，使得第一模具设置在衬底上方，并且第二模具设置在第一模具的下方。

公开(公告)号：US07091613B1

公开(公告)日：2006-08-15

申请号：US10699118

申请日：2003-10-31

申请人： Jon M. Long ,  Joseph W. Foerstel

发明人： Jon M. Long ,  Joseph W. Foerstel

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48784 ,  H01L2224/49171 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： An elongated bonding pad comprises two areas, a bonding area and an elongated probing area. The bonding area is located on the edge of an integrated circuit device for wire bonding. The elongated probing area is located on the inner area of the device. The long dimension of the elongated probing area is large enough for carrying a probing mark and the short dimension of the probing area is electrically and mechanically connected to the bonding area. Such elongated bonding pad can reduce the possibility of bonding wire open failures caused by wafer sort probing and increase the device's capacity of hosting more electrical components.

摘要翻译： 细长的接合焊盘包括两个区域，即接合区域和细长的探测区域。 接合区域位于用于引线接合的集成电路器件的边缘上。 细长的探测区域位于设备的内部区域。 细长探测区域的长尺寸足以承载探测标记，并且探测区域的短尺寸电连接和机械连接到接合区域。 这种细长的接合焊盘可以减少由晶片分类探测引起的导线打开故障的可能性，并且增加设备容纳更多电气部件的能力。

公开(公告)号：US5407275A

公开(公告)日：1995-04-18

申请号：US860932

申请日：1992-03-31

申请人： Jon M. Long

发明人： Jon M. Long

IPC分类号： G01N25/72 ,  G01R31/28 ,  G01R31/311 ,  G01R31/04

CPC分类号： G01R31/311 ,  G01N25/72 ,  G01R31/2853

摘要： A method for testing a lead connection to an integrated circuit chip is disclosed. The method comprises the steps of: (a) applying heat to an exposed surface of the integrated circuit chip; and (b) determining the heat transferred from the integrated circuit chip to a lead. Rapid transfer of heat to the lead indicates a valid connection between the integrated circuit chip and the electrical lead. Slow, non-uniform, or inadequate transfer of heat to the lead indicates an insufficiency or failure in the electrical connection between the integrated circuit and the lead. Determination of the heat transferred from the integrated circuit chip to the lead can be by any appropriate method. For example, the temperature of the lead can be determined using temperature probe, a liquid crystal display, or an electronically or visually scanned infrared display.

摘要翻译： 公开了一种用于测试到集成电路芯片的引线连接的方法。 该方法包括以下步骤：（a）向集成电路芯片的暴露表面施加热量; 和（b）确定从集成电路芯片传递到引线的热量。 将热量快速传递到引线表示集成电路芯片和电线之间的有效连接。 缓慢的，不均匀的或不足的热量传导到引线表示集成电路和引线之间的电连接不足或失败。 可以通过任何适当的方法确定从集成电路芯片传递到引线的热量。 例如，引线的温度可以使用温度探针，液晶显示器或电子或视觉扫描的红外显示器来确定。

公开(公告)号：US5349495A

公开(公告)日：1994-09-20

申请号：US592709

申请日：1990-10-04

申请人： Thomas A. Visel ,  Jon M. Long

发明人： Thomas A. Visel ,  Jon M. Long

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H01L29/06 ,  H01R9/00

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L29/0657 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10157 ,  H01L2924/30107 ,  H01L2924/3025

摘要： A system for securing and electrically connecting a semiconductor chip to a body of passive substrate. The semiconductor chip and the substrate are both provided with bonding pads or bonding areas. The bonding pads or areas are located so that when a chip is placed next to the substrate, at least some of the bonding pads on the chip are aligned with corresponding bonding areas on the substrate. Micro-pins in the shape of straight wires, stubs or loops are used to electrically connect some of the bonding pads on the chip to corresponding areas on the substrate thereby electrically connecting them and also securely bonding the chip to the substrate. In the preferred embodiment, epoxy is used to further strengthen the physical bonding between the chip and the substrate. The wicking action of the micro-pins reduces bridging of solder across adjacent micro-pins.

摘要翻译： 一种用于将半导体芯片固定并电连接到无源基板主体的系统。 半导体芯片和基板都设置有接合焊盘或接合区域。 接合焊盘或区域被定位成使得当将芯片放置在衬底旁边时，芯片上的至少一些焊盘与衬底上的对应的接合区域对准。 使用直线形状，短线或环形的微销将芯片上的一些接合焊盘电连接到基板上的相应区域，从而电连接它们，并且将芯片牢固地结合到基板。 在优选实施例中，使用环氧树脂来进一步加强芯片和基板之间的物理结合。 微引脚的芯吸作用减少了焊料跨相邻微引脚的桥接。

公开(公告)号：US5260234A

公开(公告)日：1993-11-09

申请号：US773519

申请日：1991-10-09

申请人： Jon M. Long

发明人： Jon M. Long

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L21/58 ,  H01L21/60

CPC分类号： H01L23/49582 ,  H01L21/4825 ,  H01L23/49572 ,  H01L2224/05554 ,  H01L2224/49171 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14

摘要： An interconnect structure comprising an interconnection formed between a bond pad and the end of a lead. The layer includes nickel, copper, cobalt, palladium, platinum, silver or gold and is electrically conductive. Also, an apparatus for forming an interconnection by a metal plating process and a device having a lead, a substrate, and a bath containing an aqueous metal plating solution which permits formation of the interconnect structure. A method of forming an interconnect structure including the step of placing a lead adjacent to a bond pad and placing the two in an electroless plating solution so that the interconnect structure may be formed.

摘要翻译： 一种互连结构，包括形成在接合焊盘和引线端部之间的互连。 该层包括镍，铜，钴，钯，铂，银或金并且是导电的。 另外，通过金属电镀工艺形成互连的装置和具有引线，基板和含有允许形成互连结构的金属电镀液的镀液的装置。 一种形成互连结构的方法，包括将引线放置在接合焊盘附近并将其放置在化学镀溶液中从而形成互连结构的步骤。

公开(公告)号：US5210440A

公开(公告)日：1993-05-11

申请号：US710740

申请日：1991-06-03

申请人： Jon M. Long

发明人： Jon M. Long

IPC分类号： H01L21/60 ,  H01L23/473 ,  H01L23/495

CPC分类号： H01L24/50 ,  H01L23/473 ,  H01L23/49572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14

摘要： A novel semiconductor chip cooling apparatus includes at least one semiconductor die packaged according to a TAB design. A support structure supports the die, and a dike is connected to the support structure and the TAB tape to form a cavity impervious to liquid and air. Input and output means are connected to the cavity. Fluid means circulate throughout the cavity and utilize the input and output means to directly cool the die during operation of the semiconductor die. Heat spreading means may be positioned below the die to increase the amount of surface area which contacts the fluid means, thereby cooling the die more efficiently.

摘要翻译： 一种新颖的半导体芯片冷却装置，包括至少一个根据TAB设计封装的半导体管芯。 支撑结构支撑模具，并且堤防连接到支撑结构和TAB带以形成不透液体和空气的空腔。 输入和输出装置连接到空腔。 流体装置在整个空腔中循环，并利用输入和输出装置在半导体管芯工作期间直接冷却管芯。 散热装置可以位于模具下方以增加与流体装置接触的表面积的量，从而更有效地冷却模具。

公开(公告)号：US09002155B2

公开(公告)日：2015-04-07

申请号：US13360314

申请日：2012-01-27

申请人： Peng Li ,  Sergey Shumarayev ,  Jon M. Long ,  Tien Duc Pham

发明人： Peng Li ,  Sergey Shumarayev ,  Jon M. Long ,  Tien Duc Pham

IPC分类号： G02B6/42 ,  G02B6/43 ,  G02B6/12 ,  H04J14/02 ,  H04B10/40

CPC分类号： H04J14/02 ,  G02B6/12 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H04B10/40

摘要： Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.

摘要翻译： 提供了提供具有用于高速关闭设备通信的集成光电子接口的集成电路设备电路的系统。 光电子接口可并入集成电路器件中，释放集成电路器件的部分或全部电I / O引脚。 收发器I / O通道可以设置在可以在电和光收发器I / O通道之间切换的集成电路装置上。