公开(公告)号：US08564046B2

公开(公告)日：2013-10-22

申请号：US13104377

申请日：2011-05-10

Applicant: Jin-Gyun Kim ,  Myoung-Bum Lee

Inventor： Jin-Gyun Kim ,  Myoung-Bum Lee

IPC: H01L29/792

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.

Abstract translation: 垂直半导体器件和制造垂直半导体器件的方法包括形成在衬底上的第一半导体图案和形成在第一半导体图案的侧壁上的第一栅极结构。 在第一半导体图案上形成第二半导体图案。 在第二半导体图案的侧壁上形成多个绝缘层间图案。 绝缘层间图案彼此间隔开以在绝缘层间图案之间限定凹槽。 多个第二栅极结构分别设置在沟槽中。

公开(公告)号：US07800162B2

公开(公告)日：2010-09-21

申请号：US12235689

申请日：2008-09-23

Applicant: Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

Inventor： Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

IPC: H01L29/94

CPC classification number: H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Abstract translation: 非易失性存储器件包括半导体衬底，半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的电极间绝缘层和电极上的控制栅电极 绝缘层。 电极间绝缘层包括具有大于氮化硅的介电常数的高k电介质层，以及电荷存储层和高k电介质层之间的界面层。 界面层包括氧氮化硅层。

公开(公告)号：US07696563B2

公开(公告)日：2010-04-13

申请号：US11896834

申请日：2007-09-06

Applicant: Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

Inventor： Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal.

Abstract translation: 非易失性存储器件包括在衬底的通道区域上的隧道绝缘层图案，隧道绝缘层图案上的电荷俘获层图案，电荷俘获层图案上的阻挡层图案，以及包括导电 阻挡层图案上的层图案和导电层图案上的阻挡层图案。 导电层图案包括金属。

公开(公告)号：US20080211057A1

公开(公告)日：2008-09-04

申请号：US12003973

申请日：2008-01-04

Applicant: Si-hyung Lee ,  Sang-ryol Yang ,  Myoung-bum Lee ,  Ki-hyun Hwang

Inventor： Si-hyung Lee ,  Sang-ryol Yang ,  Myoung-bum Lee ,  Ki-hyun Hwang

IPC: H01L29/40

CPC classification number: H01L27/10876 ,  H01L27/10891

Abstract: Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

Abstract translation: 提供一种具有掩埋字线结构的半导体器件，其中栅极电极和字线可以被掩埋在衬底内以降低半导体器件的高度并且减少由来自应用的氯离子引起的氧化物层的劣化 的TiN金属栅极，以及制造半导体器件的方法。 半导体器件可以包括由器件隔离层限定的半导体衬底，并且包括有源区，包括沟槽和一个或多个凹陷通道，沟槽表面上的栅极隔离层，栅极表面上的栅极电极层 隔离层以及沟槽可以埋在栅电极层的表面上的字线。

公开(公告)号：US20050095857A1

公开(公告)日：2005-05-05

申请号：US10982113

申请日：2004-11-04

Applicant: Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

Inventor： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

IPC: H01L21/28 ,  H01L21/225 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76877 ,  H01L21/2257 ,  H01L21/28525 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Abstract translation: 形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。 可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。 还讨论了相关结构。

公开(公告)号：US06849555B2

公开(公告)日：2005-02-01

申请号：US10449522

申请日：2003-05-30

Applicant: Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

Inventor： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC: C23C14/56 ,  C23C16/44 ,  H01L21/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/302 ,  H01L21/461 ,  H01L21/677 ,  H01L21/768

CPC classification number: H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

Abstract translation: 提供了可用于形成具有多层结构的金属布线层和使用其的晶片处理方法的集成的原位簇型晶片处理装置。 晶片处理装置包括可以排出并具有多个闸阀的传送室，多个真空处理室，每个真空处理室可以经由一个闸阀连接到传送室;以及负载锁定室，其可以 被排出并且可连接到用于将氧基气体进料到负载锁定室中的第一气体供给管线。 在晶片处理方法中，在一个真空处理室中的晶片上形成预定层。 晶片上的预定层在负载锁定室或氧气氛室中被氧化。

公开(公告)号：US06699790B2

公开(公告)日：2004-03-02

申请号：US10035807

申请日：2002-01-04

Applicant: Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

Inventor： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC: H01L21443

CPC classification number: H01L21/76876 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882

Abstract: A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

Abstract translation: 一种在硅衬底上的绝缘层中具有凹陷区域的半导体器件制造方法，包括以下步骤：在绝缘层的整个表面上沉积阻挡金属，用氧化物层填充该凹陷区域， 去除所述凹陷区域中的氧化物层并暴露所述凹陷区域的阻挡金属，在所述阻挡金属上沉积CVD-Al层，以及在所述CVD-Al层上沉积PVD-Al层，以及 重新流动PVD-Al层。 根据本发明的半导体集成电路的制造方法选择性地去除凹陷区域的外部的阻挡金属以将绝缘层暴露于空气，并沉积CVD-Al层和PVD-Al层，这导致 控制CVD-Al金属的异常生长。

公开(公告)号：US5656337A

公开(公告)日：1997-08-12

申请号：US296931

申请日：1994-08-31

Applicant: In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

Inventor： In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

IPC: H01L21/205 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H05H1/00

CPC classification number: H01L21/02164 ,  C23C16/0245 ,  C23C16/402 ,  C23C16/44 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31051 ,  H01L21/31608

Abstract: A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.

Abstract translation: 介电材料的沉积速率随着下层的电极性而变化，以获得优异的沉积和平坦化特性。 导电层和下面的电介质被表面处理以具有不同的电极性，使得通过使用电介质材料在导电层上和在下面的电介质之间的沉积速率的差异来形成电介质。 提供了一种具有连接在基座和其气体注入部分之间的直流电源的CVD装置。 沉积和平坦化可以在低温下进行并且在工艺上被简化。

公开(公告)号：US09343475B2

公开(公告)日：2016-05-17

申请号：US14155842

申请日：2014-01-15

Applicant: Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

Inventor： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157

Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Abstract translation: 在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。 通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。 然后，可以扩大孔的内部。 半导体图案形成为部分地填充孔的扩大部分。 可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。 然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。 在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。 牺牲层被栅电极代替。

公开(公告)号：US20150200203A1

公开(公告)日：2015-07-16

申请号：US14155842

申请日：2014-01-15

Applicant: Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

Inventor： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157

Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Abstract translation: 在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。 通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。 然后，可以扩大孔的内部。 半导体图案形成为部分地填充孔的扩大部分。 可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。 然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。 在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。 牺牲层被栅电极代替。