公开(公告)号：US20150364570A1

公开(公告)日：2015-12-17

申请号：US14304017

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Cuiqin Xu ,  Isabelle Ferain

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/32 ,  H01L29/6659 ,  H01L29/66628

Abstract: One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

Abstract translation: 本文公开的一种说明性方法包括进行源极/漏极扩展离子注入以在器件的源极/漏极区域中形成掺杂的延伸注入区域，在源极/漏极区域上执行离子注入工艺 VII材料（例如氟），在进行第VII族材料离子注入工艺之后，在源极/漏极区域上方形成覆盖材料层，并且在覆盖材料层就位的情况下，进行退火处理以形成堆垛层错 在源/漏区。

公开(公告)号：US09231079B1

公开(公告)日：2016-01-05

申请号：US14304017

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Cuiqin Xu ,  Isabelle Ferain

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L21/266

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/32 ,  H01L29/6659 ,  H01L29/66628

Abstract: One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

Abstract translation: 本文公开的一种说明性方法包括进行源极/漏极扩展离子注入以在器件的源极/漏极区域中形成掺杂的延伸注入区域，在源极/漏极区域上执行离子注入工艺 VII材料（例如氟），在进行第VII族材料离子注入工艺之后，在源极/漏极区域上方形成覆盖材料层，并且在覆盖材料层就位的情况下，进行退火处理以形成堆垛层错 在源/漏区。

公开(公告)号：US20150303295A1

公开(公告)日：2015-10-22

申请号：US14258279

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Xiang Hu ,  Jinping Liu ,  Gabriel Padron Wells ,  Andy Chih-Hung Wei ,  Guillaume Bouche ,  Cuiqin Xu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/51 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.

Abstract translation: 提供了在半导体器件（例如，FinFET器件）中形成一组接触开口的方法。 具体地，半导体器件包括形成在衬底中的一组翅片，形成在衬底上的栅极结构（例如，替换金属栅极（RMG））以及与栅极结构相邻的一组接触开口，该组接触 具有顶部和底部的开口，其中沿着栅极结构的长度的底部的宽度大于顶部的宽度。 半导体器件还包括形成在该组接触开口内的一组金属触头。

公开(公告)号：US10020383B2

公开(公告)日：2018-07-10

申请号：US14716938

申请日：2015-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jer-Hueih(James) Chen ,  Cuiqin Xu ,  Padmaja Nagaiah

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/28008 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

公开(公告)号：US09741853B2

公开(公告)日：2017-08-22

申请号：US14926897

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mantavya Sinha ,  Prasanna Kannan ,  Cuiqin Xu ,  Tao Wang ,  Suresh Kumar Regonda

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324

CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/324 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847

Abstract: Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.

公开(公告)号：US09129987B2

公开(公告)日：2015-09-08

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jin Ping Liu ,  Guillaume Bouche ,  Andy Wei ,  Lakshmanan H. Vanamurthy ,  Cuiqin Xu ,  Sridhar Kuchibhatla ,  Rama Kambhampati ,  Xiuyu Cai

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧上沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US20150214345A1

公开(公告)日：2015-07-30

申请号：US14164368

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jinping Liu ,  Churamani Gaire ,  Mariappan Hariharaputhiran ,  Andy Chih-Hung Wei ,  Bharat V. Krishnan ,  Cuiqin Xu ,  Michael Ganz

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/88 ,  H01L29/73 ,  H01L21/306 ,  H01L29/161 ,  H01L29/06 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66151 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7311 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/88

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.

Abstract translation: 提供了用于在集成电路（IC）器件（例如，金属氧化物半导体场效应晶体管（MOSFET））中隔离源极和漏极区域的方法。 具体地，该器件包括形成在衬底上的栅极结构，与栅极结构相邻嵌入在衬底内的源极和漏极（S / D）以及S / D和衬底之间的衬里层（例如，硅 - 碳） 。 在一种方法中，衬垫层也形成在S / D的顶部。 因此，形成在接合部中的衬垫层防止掺杂剂从源极/漏极扩散。