公开(公告)号：US09536985B2

公开(公告)日：2017-01-03

申请号：US14499356

申请日：2014-09-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Brian J. Greene ,  Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Renee T. Mo ,  Yinxiao Yang

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/7848

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract translation: 一种用于制造半导体结构的方法以及半导体结构，其使用半导体鳍周围的绝缘层的部分去除，并且随后在暴露区域中外延生长另外的半导体材料，同时保持鳍的形状，同时保持鳍的形状 绝缘层。

公开(公告)号：US09349650B2

公开(公告)日：2016-05-24

申请号：US14524246

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Yue Ke ,  Annie Levesque ,  Dae-Gyu Park ,  Ravikumar Ramachandran ,  Amanda L. Tessier ,  Min Yang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/26566 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853

Abstract: A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.

Abstract translation: 栅极结构跨越从绝缘体层的最上表面向上延伸的多个半导体鳍片的第一部分形成。 介电隔离件形成在栅极结构的侧壁上并且跨越多个半导体鳍片的第二部分。 至少从不包括栅极结构或栅极间隔物的半导体鳍片的暴露的侧壁至少生长包括非平面最底表面和非平面最上表面的外延半导体材料部分，以使相邻的半导体鳍片合流。 在外延半导体材料部分和绝缘体层的最上表面之下存在间隙。 在外延半导体材料部分上形成第二外延半导体材料，然后将第二外延半导体材料转换成金属半导体合金。

公开(公告)号：US20190113469A1

公开(公告)日：2019-04-18

申请号：US15786986

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Oliver D. Patterson ,  Richard F. Hafer ,  Dave M. Salvador ,  Yue Ke

IPC: G01N23/22 ,  H01J37/21 ,  G01N23/225 ,  H01J37/20

Abstract: A method of inspecting semiconductors and a semiconductor inspection system are disclosed. In an embodiment, the method comprises directing a charged particle beam onto a semiconductor device at an angle in a range between five degrees and eighty-five degrees from a normal to a top surface of the semiconductor; scanning the particle beam across a field of the semiconductor device; adjusting the semiconductor to maintain the particle beam at a defined focus on the semiconductor while scanning the particle beam across the field of the semiconductor device; detecting secondary and backscattered electrons from the semiconductor; and processing the detected secondary and backscattered electrons to inspect for defined conditions of the semiconductor. In an embodiment, the particle beam is maintained at the defined focus on the semiconductor device by controlling the position of the semiconductor device relative to a beam emitter that emits the particle beam.

公开(公告)号：US09875939B1

公开(公告)日：2018-01-23

申请号：US15373129

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yue Ke ,  Alexander Reznicek ,  Benjamin Moser ,  Dominic J. Schepis ,  Melissa A. Smith ,  Henry K. Utomo ,  Reinaldo Vega ,  Sameer Jain

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/266 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66795

Abstract: Methods of fabricating integrated circuit devices for forming uniform and well controlled fin recesses are disclosed. One method includes, for instance: obtaining an intermediate semiconductor structure having a substrate, at least one fin disposed on the substrate, at least one gate structure positioned over the at least one fin, and at least one oxide layer disposed on the substrate and about the at least one fin and the at least one gate structure; implanting germanium (Ge) in a first region of the at least one fin; and removing the first region of the at least one fin implanted with Ge.

公开(公告)号：US09634084B1

公开(公告)日：2017-04-25

申请号：US15040477

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christopher D. Sheraw ,  Chengwen Pei ,  Eric T. Harley ,  Yue Ke ,  Henry K. Utomo ,  Yinxiao Yang ,  Zhibin Ren

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0615 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

公开(公告)号：US09577099B2

公开(公告)日：2017-02-21

申请号：US14641917

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Eric C. T. Harley ,  Yue Ke ,  Alexander Reznicek ,  Henry K. Utomo

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/04 ,  H01L29/45 ,  H01L21/306

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract translation: 半导体结构包括半导体衬底上的翅片。 通过在翅片侧壁和翅片的上表面上形成缓冲层来提供干净的外延生长表面。 缓冲层可以外延生长。 菱形外延从缓冲层侧壁生长。 在一些实施方案中，钻石形外延可以随后与周围的电介质合并。 周围电介质的掺杂剂浓度可高于菱形外延的掺杂剂浓度。

公开(公告)号：US09246003B2

公开(公告)日：2016-01-26

申请号：US14083517

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Yue Ke ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

Abstract translation: 半导体结构可以包括半导体鳍片，半导体鳍片上的栅极，栅极的侧壁上的间隔物，在间隔物下方的半导体鳍片的端部中的成角度的凹陷区域以及填充成角度的凹部的第一半导体区域。 成角度的凹槽可以是v形或西格玛形。 该结构还可以包括与第一半导体区域和衬底接触的第二半导体区域。 该结构可以通过在衬底上形成半导体翅片的一部分上方的栅极形成，在栅极的侧壁上形成间隔物; 除去未被间隔物或栅极覆盖的半导体鳍片的一部分以暴露翅片的侧壁，蚀刻翅片的侧壁以在间隔物下方形成倾斜的凹陷区域，并用第一外延半导体填充成角度的凹陷区域 地区。

公开(公告)号：US09577100B2

公开(公告)日：2017-02-21

申请号：US14305543

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Kern Rim ,  Henry K. Utomo

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract translation: 一种半导体器件，包括至少一个包含硅的悬浮沟道结构，以及存在于悬挂沟道结构上的栅极结构。 至少一个栅极电介质层存在于悬置沟道结构周围，并且至少一个栅极导体存在于至少一个栅极电介质层上。 源极和漏极结构可以由包括硅和锗的材料组成。 源极和漏极结构通过硅包覆层与悬浮沟道结构的源极和漏极端部接触。

公开(公告)号：US09466616B2

公开(公告)日：2016-10-11

申请号：US15054951

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.

公开(公告)号：US20160268413A1

公开(公告)日：2016-09-15

申请号：US14641917

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Eric C. T. Harley ,  Yue Ke ,  Alexander Reznicek ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract translation: 半导体结构包括半导体衬底上的翅片。 通过在翅片侧壁和翅片的上表面上形成缓冲层来提供干净的外延生长表面。 缓冲层可以外延生长。 菱形外延从缓冲层侧壁生长。 在一些实施方案中，钻石形外延可以随后与周围的电介质合并。 周围电介质的掺杂剂浓度可高于菱形外延的掺杂剂浓度。