公开(公告)号：US20170176495A1

公开(公告)日：2017-06-22

申请号：US14976808

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Wen Yin ,  Anna M. Prakash ,  Teag R. Haughan ,  Dingying David Xu ,  Joaquin Aguilar-Santillan

IPC: G01R1/067 ,  C25D3/54 ,  C25D5/34 ,  C25D5/50 ,  C23C8/20 ,  C22F1/18 ,  C11D7/28 ,  C25D7/00

CPC classification number: G01R1/06761 ,  C11D11/0047 ,  C22F1/183 ,  C23C8/16 ,  C23C8/20 ,  C23C8/80 ,  C25D3/54 ,  C25D5/34 ,  C25D5/50 ,  C25D7/00 ,  G01R1/06722

Abstract: Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.

公开(公告)号：US11676891B2

公开(公告)日：2023-06-13

申请号：US17364686

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Dingying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/49816 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US12230563B2

公开(公告)日：2025-02-18

申请号：US17956769

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Dingying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20170176516A1

公开(公告)日：2017-06-22

申请号：US14976881

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Mohit Mamodia ,  Kyle Yazzie ,  Dingying David Xu ,  Kuang Liu ,  Paul J. Diglio ,  Pramod Malatkar

IPC: G01R31/28 ,  H05B3/26

CPC classification number: H05B3/267 ,  G01R31/2867 ,  G01R31/2875

Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

公开(公告)号：US11088062B2

公开(公告)日：2021-08-10

申请号：US15654399

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Dingying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US10168357B2

公开(公告)日：2019-01-01

申请号：US14976808

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Wen Yin ,  Anna M. Prakash ,  Teag R. Haughan ,  Dingying David Xu ,  Joaquin Aguilar-Santillan

IPC: G01R1/067 ,  C25D3/54 ,  C25D7/00 ,  C25D5/50 ,  C23C8/20 ,  C22F1/18 ,  C25D5/34 ,  C11D11/00

Abstract: Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.

公开(公告)号：US09659889B2

公开(公告)日：2017-05-23

申请号：US14136908

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Mihir Oka ,  Xavier Brun ,  Dingying David Xu ,  Edward Prack ,  Kabirkumar Mirpuri ,  Saikumar Jayaraman

IPC: H01L23/00 ,  C08K3/36 ,  C08K3/22 ,  B23K1/20 ,  B23K1/00 ,  B23K26/362 ,  C09D179/02 ,  C08G73/02 ,  B23K101/42

CPC classification number: H01L24/11 ,  B23K1/0016 ,  B23K1/20 ,  B23K26/361 ,  B23K26/362 ,  B23K2101/42 ,  C08G73/0233 ,  C08K3/22 ,  C08K3/36 ,  C08K2003/2241 ,  C09D179/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  C08L79/04 ,  C08L79/02

Abstract: This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.