公开(公告)号：US12230536B1

公开(公告)日：2025-02-18

申请号：US17559490

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  Eungnak Han ,  Manish Chandhok ,  Gurpreet Singh

IPC: H01L21/768 ,  H01L23/522

Abstract: Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

公开(公告)号：US12037434B2

公开(公告)日：2024-07-16

申请号：US17313932

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20240203868A1

公开(公告)日：2024-06-20

申请号：US18066301

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  David Nathan Shykind ,  Richard E. Schenker ,  Florian Gstrein ,  Eungnak Han ,  Nafees Aminul Kabir ,  Sean Michael Pursel ,  Nityan Labros Nair ,  Robert Seidel

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76879

Abstract: Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.

公开(公告)号：US20240194672A1

公开(公告)日：2024-06-13

申请号：US18064362

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Bharath Bangalore Rajeeva ,  Manish Chandhok ,  Gurpreet Singh ,  Kevin Huggins ,  Eungnak Han ,  Florian Gstrein ,  Marko Radosavljevic

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L23/522 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0271 ,  H01L23/5226 ,  H01L29/1033 ,  H01L29/42364

Abstract: An IC device may include a first conductive structure in a first section and a second conductive structure in a second section. The second conductive structure is in parallel with the first conductive structure in a first direction. A dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction. The first conductive structure may be coupled to a channel region of a transistor. The second conductive structure may be coupled to a channel region of another transistor. A first structure comprising a first dielectric material may be over the first conductive structure. A second structure comprising a second dielectric material may be over the second section. A third structure comprising the first dielectric material may be over the second conductive structure and be at least partially surrounded by the second structure.

公开(公告)号：US20240186264A1

公开(公告)日：2024-06-06

申请号：US18061083

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Yi Yang ,  Eungnak Han ,  Suddhasattwa Nad ,  Marcel A. Wall

IPC: H01L23/00 ,  B32B17/10 ,  C09D201/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/562 ,  B32B17/10 ,  C09D201/00 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  B32B2255/10 ,  B32B2255/205 ,  B32B2270/00 ,  B32B2307/732 ,  B32B2457/08

Abstract: In one embodiment, an apparatus includes a glass substrate, a metal, and a polymeric layer between the metal and the glass substrate. The polymeric layer includes polymer molecules with an R1 group, an R2 group, a polymer backbone between the R1 group and R2 group, and an R3 group side-attached to the polymer backbone. The polymeric layer is bonded to the glass substrate via the R1 groups and bonded to the metal via the R2 groups.

公开(公告)号：US11251117B2

公开(公告)日：2022-02-15

申请号：US16562346

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US10459338B2

公开(公告)日：2019-10-29

申请号：US15480208

申请日：2017-04-05

Applicant: Intel Corporation

Inventor： Paul A. Nyhus ,  Eungnak Han ,  Swaminathan Sivakumar ,  Ernisse S. Putna

IPC: G03F7/039 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/768 ,  G03F7/00 ,  G03F7/004 ,  G03F7/038 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/3205 ,  H01L21/3213 ,  B81C1/00

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.

公开(公告)号：US10109583B2

公开(公告)日：2018-10-23

申请号：US15529483

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Robert L. Bristol ,  Manish Chandhok ,  Jasmeet S. Chawla ,  Florian Gstrein ,  Eungnak Han ,  Rami Hourani ,  Kevin Lin ,  Richard E. Schenker ,  Todd R. Younkin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

公开(公告)号：US09570349B2

公开(公告)日：2017-02-14

申请号：US15237542

申请日：2016-08-15

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Rami Hourani ,  Eungnak Han ,  James M. Blackwell

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基底的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：US12293913B1

公开(公告)日：2025-05-06

申请号：US17559363

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Richard E. Schenker ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Gauri Nabar ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L23/532 ,  H01L21/027

Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.