中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

101 records (took 0.031 seconds)

    Instructions processors, methods, and systems to process secure hash algorithms
    1.
    发明授权
    Instructions processors, methods, and systems to process secure hash algorithms 有权

    公开(公告)号：US10911222B2

    公开(公告)日：2021-02-02

    申请号：US16807021

    申请日：2020-03-02

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

    IPC: H04L9/06 ,  G06F21/64 ,  G06F9/30 ,  G06F21/72 ,  G06F21/60

    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

    Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match
    3.
    发明授权
    Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match 有权

    公开(公告)号：US10509580B2

    公开(公告)日：2019-12-17

    申请号：US15089456

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford ,  Sean M. Gulley

    IPC: G06F3/06 ,  G06F12/00 ,  H03M7/30

    Abstract: Methods and apparatuses relating to memory compression and decompression are described, including a memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match. When indices for multiple sections are the same, an entry in the dictionary may be updated with the value of the section that is most recent, in the same order as in the block of data. In one embodiment, a hardware compression engine is to determine when each section of a plurality of sections of a block of data is a zero value, a full match or a partial match to an entry in a dictionary, or a no match to any entry in the dictionary, encode a tag for each section to indicate the one of the zero value, the full match, the partial match, and the no match, encode a literal when the section is the no match, an index to the entry in the dictionary when the section is the full match, and an index to the entry in the dictionary and non-matching bits when the section is the partial match, and update an entry in the dictionary with a value of a section when the section is the no match, wherein tags for the plurality of sections are to be output from the hardware compression engine in a single field, literals for the plurality of sections are to be output from the hardware compression engine in a single field, indexes for the plurality of sections are to be output from the hardware compression engine in a single field, and non-matching bits for the plurality of sections are to be output from the hardware compression engine in a single field. A hash value may be generated for each of a plurality of sections of a block of data to use as an index in a dictionary.

    SMS4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    8.
    发明申请
    SMS4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
    SMS4加速处理器，方法，系统和指令

    公开(公告)号：US20150186138A1

    公开(公告)日：2015-07-02

    申请号：US14142724

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F9/30 ,  G06F21/60

    CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3895 ,  G06F21/602 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

    Abstract: A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.

    Abstract translation: 一方面的处理器包括多个打包数据寄存器和用于解码指令的解码单元。 该指令是指示一个或多个源打包数据操作数。 一个或多个源打包数据操作数具有四个先前的SMS4回合的四个32位结果。 一个或多个源操作数也具有32位值。 执行单元与解码单元和多个打包数据寄存器耦合。 执行单元响应于该指令，将当前SMS4的32位结果存储在要由指令指示的目的地存储单元中。

    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY
    9.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY 有权

    公开(公告)号：US20210036848A1

    公开(公告)日：2021-02-04

    申请号：US16928558

    申请日：2020-07-14

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
    10.
    发明授权
    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality 有权

    公开(公告)号：US10778425B2

    公开(公告)日：2020-09-15

    申请号：US16223109

    申请日：2018-12-17

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Patent Agency Ranking