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公开(公告)号：US10459858B2
公开(公告)日：2019-10-29
申请号：US15804939
申请日：2017-11-06
Applicant: INTEL CORPORATION
Inventor： Hong Wang , Per Hammarlund , Xiang Zou , John P. Shen , Xinmin Tian , Milind Girkar , Perry H. Wang , Piyush N. Desai
Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.
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公开(公告)号：US09785576B2
公开(公告)日：2017-10-10
申请号：US14227178
申请日：2014-03-27
Applicant: Intel Corporation
Inventor： Thiam Wah Loh , Per Hammarlund , Andreas Wasserbauer , Swee Chong Peter Kuan , Eckhard Delfs , Deepak A. Mathaikutty , Stephen J. Robinson , Gautham N. Chinya , Perry H. Wang , Chee Weng Tan , Hong Wang , Reza Fortas
CPC classification number: G06F12/1408 , G06F12/1491 , G06F21/10 , G06F21/575 , G06F2212/1052 , G06F2221/032 , Y02D10/13
Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.
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公开(公告)号：US08812792B2
公开(公告)日：2014-08-19
申请号：US14033463
申请日：2013-09-21
Applicant: Intel Corporation
Inventor： Quinn A. Jacobson , Anne W. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Shinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
CPC classification number: G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
Abstract translation: 使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。
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公开(公告)号：US09600283B2
公开(公告)日：2017-03-21
申请号：US14854082
申请日：2015-09-15
Applicant: INTEL CORPORATION
Inventor： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
CPC classification number: G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
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公开(公告)号：US09032232B2
公开(公告)日：2015-05-12
申请号：US13786939
申请日：2013-03-06
Applicant: Intel Corporation
Inventor： Martin G. Dixon , Scott D. Rodgers , Taraneh Bahrami , Stephen H. Gunther , Prashant Sethi , Per Hammarlund
CPC classification number: G06F1/3234 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3293 , G06F9/30083 , G06F9/3009 , Y02D10/122 , Y02D50/20
Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09990206B2
公开(公告)日：2018-06-05
申请号：US13843164
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Hong Wang , John Shen , Edward Grochowski , Richard Hankins , Gautham Chinya , Bryant Bigbee , Shivnandan Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggawal , Prashant Sethi , Baiju Patel , James Held
CPC classification number: G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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7.发明申请MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS 审中-公开用于指导性设计的机构执行多个指令序列公开(公告)号：US20170010895A1
公开(公告)日：2017-01-12
申请号：US15276290
申请日：2016-09-26
Applicant: Intel Corporation
Inventor： Hong Wang , John P. Shen , Edward T. Grochowski , Richard A. Hankins , Gautham N. Chinya , Bryant E. Bigbee , Shivnandan D. Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggarwal , Prashant Sethi , Baiju V. Patel , James P. Held
CPC classification number: G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。
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8.发明申请Methods And Apparatuses For Reducing Power Consumption Of Processor Switch Operations 审中-公开降低处理器开关操作功耗的方法和装置公开(公告)号：US20160004533A1
公开(公告)日：2016-01-07
申请号：US14854082
申请日：2015-09-15
Applicant: INTEL CORPORATION
Inventor： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
CPC classification number: G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。
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公开(公告)号：US08990597B2
公开(公告)日：2015-03-24
申请号：US13891747
申请日：2013-05-10
Applicant: Intel Corporation
Inventor： Martin G. Dixon , Scott D. Rodgers , Taraneh Bahrami , Stephen H. Gunther , Prashant Sethi , Per Hammarlund
CPC classification number: G06F1/3234 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3293 , G06F9/30083 , G06F9/3009 , Y02D10/122 , Y02D50/20
Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于 定时器值。 处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。 描述和要求保护其他实施例。
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10.发明申请Instruction Set Architecture-Based Inter-Sequencer Communications With A Heterogeneous Resource 审中-公开指令集基于异构资源的基于架构的间隔符间通信公开(公告)号：US20150070368A1
公开(公告)日：2015-03-12
申请号：US14541933
申请日：2014-11-14
Applicant: Intel Corporation
Inventor： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
CPC classification number: G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器是相对于指令定序器的异构资源。 可以使用接口来提供这些资源之间的通信。 通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。 此外，指令定序器和加速器可以并行地执行操作。 描述和要求保护其他实施例。
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