公开(公告)号：US06673718B1

公开(公告)日：2004-01-06

申请号：US10305244

申请日：2002-11-27

申请人： Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

发明人： Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.

摘要翻译： 在基板的接触孔或凹槽内选择性地形成铝布线。 包含氮的中间层形成在基板的主表面上并在接触孔或凹槽的内表面上方。 用等离子体处理位于基板的主表面上方的中间层的第一表面部分，以在中间层的第一表面部分处形成被动层。 然后，没有中间真空断裂，铝膜仅沉积在中间层的位于接触孔或凹槽的内表面上方的第二表面部分上。 中间层的第一表面部分的等离子体处理防止铝膜在中间层的第一表面部分上的CAD沉积。

公开(公告)号：US06905960B2

公开(公告)日：2005-06-14

申请号：US10657140

申请日：2003-09-09

申请人： Hong-Mi Park ,  Jong-Sik Chun ,  Hyeon-Deok Lee ,  In-Sun Park ,  Jong-Myeong Lee ,  Ju-Cheol Shin

发明人： Hong-Mi Park ,  Jong-Sik Chun ,  Hyeon-Deok Lee ,  In-Sun Park ,  Jong-Myeong Lee ,  Ju-Cheol Shin

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76843 ,  H01L21/76871

摘要： In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

摘要翻译： 在半导体器件中形成接触的方法中，在半导体衬底上形成绝缘层。 然后，通过选择性地蚀刻绝缘层形成接触孔。 阻挡金属层沉积在接触孔的侧表面和底表面上，并且在绝缘层的顶表面上沉积到均匀的厚度。 在阻挡金属层上沉积抗氧化金属材料的润湿层。 在润湿层上形成金属层，并填充接触孔，从而在半导体器件中形成接触。

公开(公告)号：US20050035458A1

公开(公告)日：2005-02-17

申请号：US10945992

申请日：2004-09-22

申请人： Jong-Myeong Lee ,  In-Sun Park ,  Jong-Sik Chun

发明人： Jong-Myeong Lee ,  In-Sun Park ,  Jong-Sik Chun

IPC分类号： C23C16/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76888 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a metal film including forming a metal barrier layer on a surface of a substrate, on a bottom surface of a recess and on sidewalls of the recess, forming a first metal film on the substrate but not in the recess, treating the first metal film with nitrogen plasma to form an insulation film including nitrogen, forming a second metal film on a portion of the metal barrier layer in the recess, and forming a third metal film on the substrate, the recess and the insulation film.

公开(公告)号：US06844627B2

公开(公告)日：2005-01-18

申请号：US10367916

申请日：2003-02-19

申请人： Jong-Myeong Lee ,  In-Sun Park ,  Jong-Sik Chun

发明人： Jong-Myeong Lee ,  In-Sun Park ,  Jong-Sik Chun

IPC分类号： C23C16/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76888 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a metal film including forming a metal barrier layer on a surface of a substrate, on a bottom surface of a recess and on sidewalls of the recess, forming a first metal film on the substrate but not in the recess, treating the first metal film with nitrogen plasma to form an insulation film including nitrogen, forming a second metal film on a portion of the metal barrier layer in the recess, and forming a third metal film on the substrate, the recess and the insulation film.

摘要翻译： 一种用于形成金属膜的方法，包括在基板的表面上，在凹部的底表面和凹部的侧壁上形成金属阻挡层，在基板上形成第一金属膜而不在凹部中， 具有氮等离子体的第一金属膜以形成包括氮的绝缘膜，在所述凹部中的所述金属阻挡层的一部分上形成第二金属膜，并在所述基板，所述凹部和所述绝缘膜上形成第三金属膜。

公开(公告)号：US08889543B2

公开(公告)日：2014-11-18

申请号：US13795807

申请日：2013-03-12

申请人： Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

发明人： Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

摘要： A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

摘要翻译： 制造半导体器件的方法包括在衬底上形成开关器件。 在具有开关装置的基板中形成下部结构。 下导电层形成在下结构上。 牺牲掩模图案形成在下导电层上。 通过使用牺牲掩模图案作为蚀刻掩模蚀刻下导电层来形成下导电图案。 在具有较低导电图案的基板上形成层间绝缘层。 通过平坦化层间绝缘层直到牺牲掩模图案曝光来形成层间绝缘图案。 通过去除暴露的牺牲掩模图案来形成露出下导电图案的开口。 在开口中形成与下导电图案自对准的上导电图案。

公开(公告)号：US09355851B2

公开(公告)日：2016-05-31

申请号：US13588393

申请日：2012-08-17

申请人： Jong-Won Hong ,  Hei-Seung Kim ,  Kyoung-hee Nam ,  In-sun Park ,  Jong-Myeong Lee

发明人： Jong-Won Hong ,  Hei-Seung Kim ,  Kyoung-hee Nam ,  In-sun Park ,  Jong-Myeong Lee

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/288 ,  H01L23/532 ,  H01L27/115 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L21/76879 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53238 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

摘要翻译： 半导体器件包括填充通过衬底上的绝缘中间层的至少一部分形成并包括铜的沟槽的金属图案，以及金属图案中的包含钽，氮化钽，钛，钛中的至少一种的润湿改善层图案 氮化物，钌，钴和锰。

公开(公告)号：US20120120728A1

公开(公告)日：2012-05-17

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US08547747B2

公开(公告)日：2013-10-01

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C16/04

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅极电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。