摘要:
A new method of forming a buried contact junction in a process involving shallow trench isolation is described. A first silicon oxide layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. An opening is etched in the first silicon nitride and pad oxide layers where they are not covered by a mask. The substrate underlying the opening is etched into to form a shallow trench. An oxide material is deposited over the surface of the first silicon nitride layer and within the shallow trench and planarized to the surface of the first silicon nitride layer wherein the oxide material forms a STI region. The first silicon nitride layer is removed whereby the STI protrudes above the pad oxide layer. The pad oxide layer is removed whereby the corners of the STI above the substrate are also removed. A second silicon nitride layer is deposited overlying a sacrificial oxide layer and etched away to leave silicon nitride spacers filling in and rounding the corners of the STI. The sacrificial oxide layer is removed. A gate electrode and source/drain regions are formed in and on the substrate wherein a source/drain is adjacent to the STI. The gate electrode and STI are covered with an insulating layer. An opening is etched through the insulating layer to the source/drain region wherein the silicon nitride spacer at the corner of the STI prevents etching of the STI. The opening is filled with a conducting layer to complete formation of a contact.
摘要:
This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.
摘要:
A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer.
摘要:
Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.
摘要:
A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.
摘要:
Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material.
摘要:
Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.
摘要:
The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.
摘要:
Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
摘要:
The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.