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公开(公告)号:US10236274B2
公开(公告)日:2019-03-19
申请号:US15609242
申请日:2017-05-31
Applicant: Renesas Electronics Corporation
Inventor: Yukihiro Sato , Katsuhiko Funatsu , Takamitsu Kanazawa , Masahiro Koido , Hiroyoshi Taya
IPC: H01L23/48 , H01L21/44 , H01L25/065 , H01L23/498 , H01L25/07 , H01L23/00 , H01L23/049 , H01L21/48 , H01L23/373 , H01L25/16 , H01L25/18 , H02M7/219 , H01L23/24
Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.
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公开(公告)号:US09698125B2
公开(公告)日:2017-07-04
申请号:US14863837
申请日:2015-09-24
Applicant: Renesas Electronics Corporation
Inventor: Yukihiro Sato , Katsuhiko Funatsu , Takamitsu Kanazawa , Masahiro Koido , Hiroyoshi Taya
IPC: H01L23/48 , H01L21/44 , H01L25/065 , H01L23/498 , H01L25/07 , H01L23/00 , H01L23/049 , H01L21/48 , H01L23/373 , H01L25/16 , H01L25/18 , H02M7/219 , H01L23/24
CPC classification number: H01L25/0655 , H01L21/4846 , H01L23/049 , H01L23/24 , H01L23/3735 , H01L23/49838 , H01L23/49844 , H01L23/49861 , H01L24/09 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L25/16 , H01L25/18 , H01L2224/0603 , H01L2224/0905 , H01L2224/32225 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48227 , H01L2224/4846 , H01L2224/48472 , H01L2224/49111 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2924/13055 , H01L2924/13091 , H01L2924/16151 , H01L2924/16251 , H01L2924/181 , H02M7/219 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.
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公开(公告)号:US09230831B2
公开(公告)日:2016-01-05
申请号:US14613179
申请日:2015-02-03
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Yukihiro Sato , Nobuya Koike
IPC: H01L21/44 , H01L21/48 , H01L21/56 , H01L23/495 , H01L21/58 , H01L23/00 , H01L23/433 , H01L25/065
CPC classification number: H01L21/561 , H01L23/3107 , H01L23/4334 , H01L23/49503 , H01L23/49517 , H01L23/49541 , H01L23/49575 , H01L24/24 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L2224/05554 , H01L2224/291 , H01L2224/32245 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48245 , H01L2224/48247 , H01L2224/48463 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/73265 , H01L2224/85181 , H01L2224/85205 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2924/10162 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/386 , H01L2924/00012 , H01L2924/014 , H01L2924/00014 , H01L2924/00
Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.
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公开(公告)号:US09214412B2
公开(公告)日:2015-12-15
申请号:US14304945
申请日:2014-06-15
Applicant: Renesas Electronics Corporation
Inventor: Katsuhiko Funatsu , Yukihiro Sato , Yuichi Yato , Tomoaki Uno
IPC: H01L23/495 , H01L23/10 , H01L23/00 , H01L23/31 , H01L21/56
CPC classification number: H01L23/564 , H01L21/4825 , H01L21/4828 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/3107 , H01L23/49503 , H01L23/4952 , H01L23/49524 , H01L23/49537 , H01L23/49541 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/97 , H01L2224/05554 , H01L2224/0603 , H01L2224/40095 , H01L2224/40245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/12042 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.
Abstract translation: 半导体器件包括第一芯片安装部分,布置在第一芯片安装部分上的第一半导体芯片,形成在第一半导体芯片的表面中的第一焊盘,用作外部耦合端子的第一引线,第一导电部件 其电连接第一焊盘和第一引线,以及密封体,其密封第一芯片安装部分,第一半导体芯片,第一引线的一部分和第一导电构件的一部分。 第一导电构件包括第一板状部分和与第一板状部分一体形成的第一支撑部分。 第一支撑部的端部从密封体露出,第一支撑部形成有第一弯曲部。
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公开(公告)号:US09029197B2
公开(公告)日:2015-05-12
申请号:US14037360
申请日:2013-09-25
Applicant: Renesas Electronics Corporation
Inventor: Katsuhiko Funatsu , Tomoaki Uno , Toru Ueguri , Yukihiro Sato
CPC classification number: H01L25/50 , H01L21/4835 , H01L21/4839 , H01L21/56 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L23/3107 , H01L23/495 , H01L23/49503 , H01L23/49537 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49575 , H01L24/34 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/83 , H01L24/97 , H01L25/18 , H01L2221/68327 , H01L2221/68331 , H01L2224/05554 , H01L2224/0603 , H01L2224/29139 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/83851 , H01L2224/84801 , H01L2224/92247 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
Abstract translation: 为了提高将带施加到基板的后表面上的带的可靠性,同时确保施加到基板的后表面的带的耐热性。 在支撑构件中设置的沟槽的底表面和驱动器IC芯片的上表面之间存在间隙。 另一方面,引线框架的上表面侧由支撑构件支撑,使得沟槽的底表面接触安装在低MOS芯片上的低MOS片的上表面。 因此,即使在驱动IC芯片和Low-MOS芯片安装在引线框架的上表面侧的状态下,也可以将带子可靠地施加到引线框架的后表面(特别是后端) 产品区域的表面)。
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公开(公告)号:US08975733B2
公开(公告)日:2015-03-10
申请号:US13771235
申请日:2013-02-20
Applicant: Renesas Electronics Corporation
Inventor: Yukihiro Sato , Nobuya Koike
IPC: H01L23/495 , H01L21/58 , H01L23/00 , H01L23/433 , H01L25/065
CPC classification number: H01L21/561 , H01L23/3107 , H01L23/4334 , H01L23/49503 , H01L23/49517 , H01L23/49541 , H01L23/49575 , H01L24/24 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L2224/05554 , H01L2224/291 , H01L2224/32245 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48245 , H01L2224/48247 , H01L2224/48463 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/73265 , H01L2224/85181 , H01L2224/85205 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2924/10162 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/386 , H01L2924/00012 , H01L2924/014 , H01L2924/00014 , H01L2924/00
Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.
Abstract translation: 提供了一种能够提高通过物理地固定单独形成的芯片安装部分和引线框而制造的半导体器件的可靠性的技术。 实施例的特征在于,形成在悬挂引线中的第二接合部嵌入到形成在芯片安装部分中的第一接合部分中,从而物理地固定芯片安装部分和悬架引线。 具体而言,第一接合部由设置在芯片安装部的表面的凹部形成。 第二接合部分形成悬挂引线的一部分。
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公开(公告)号:US20150001699A1
公开(公告)日:2015-01-01
申请号:US14304945
申请日:2014-06-15
Applicant: Renesas Electronics Corporation
Inventor: Katsuhiko Funatsu , Yukihiro Sato , Yuichi Yato , Tomoaki Uno
IPC: H01L23/495
CPC classification number: H01L23/564 , H01L21/4825 , H01L21/4828 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/3107 , H01L23/49503 , H01L23/4952 , H01L23/49524 , H01L23/49537 , H01L23/49541 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/97 , H01L2224/05554 , H01L2224/0603 , H01L2224/40095 , H01L2224/40245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/12042 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.
Abstract translation: 半导体器件包括第一芯片安装部分,布置在第一芯片安装部分上的第一半导体芯片,形成在第一半导体芯片的表面中的第一焊盘,用作外部耦合端子的第一引线,第一导电部件 其电连接第一焊盘和第一引线,以及密封体,其密封第一芯片安装部分,第一半导体芯片,第一引线的一部分和第一导电构件的一部分。 第一导电构件包括第一板状部分和与第一板状部分一体形成的第一支撑部分。 第一支撑部的端部从密封体露出,第一支撑部形成有第一弯曲部。
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公开(公告)号:US11444010B2
公开(公告)日:2022-09-13
申请号:US17060545
申请日:2020-10-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Kazunori Hasegawa , Yuichi Yato , Hiroyuki Nakamura , Yukihiro Sato , Hiroya Shimoyama
Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.
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公开(公告)号:US10777490B2
公开(公告)日:2020-09-15
申请号:US16684897
申请日:2019-11-15
Applicant: Renesas Electronics Corporation
Inventor: Yukihiro Sato , Toshinori Kiyohara
IPC: H01L23/00 , H01L23/495 , H01L23/31
Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
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公开(公告)号:US20200091046A1
公开(公告)日:2020-03-19
申请号:US16684897
申请日:2019-11-15
Applicant: Renesas Electronics Corporation
Inventor: Yukihiro Sato , Toshinori Kiyohara
IPC: H01L23/495 , H01L23/00 , H01L23/31
Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
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