公开(公告)号：US11913121B2

公开(公告)日：2024-02-27

申请号：US16991999

申请日：2020-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Yi Wu ,  Chun-Hung Lu

IPC: C23F1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H05K3/10

CPC classification number: C23F1/00 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49827 ,  H05K3/108 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  Y10T29/49165 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

公开(公告)号：US20190287928A1

公开(公告)日：2019-09-19

申请号：US16360511

申请日：2019-03-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US10236227B2

公开(公告)日：2019-03-19

申请号：US14998324

申请日：2015-12-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Shan Chuang ,  Ching-Wen Chiang ,  Tzung-Yen Wu ,  Chun-Hung Lu

IPC: H01L21/00 ,  H01L23/053 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.

公开(公告)号：US20160050753A1

公开(公告)日：2016-02-18

申请号：US14739026

申请日：2015-06-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Ching Chan ,  Chien-Min Lin ,  Po-Yi Wu ,  Chun-Hung Lu

IPC: H05K1/11 ,  H05K3/42 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/112 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/423 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having opposite first and second sides and a plurality of conductive through holes communicating the first and second sides; forming an insulating layer on the first side of the substrate body, wherein the insulating layer has a plurality of openings correspondingly exposing the conductive through holes; and forming a plurality of conductive pads in the openings of the insulating layer, wherein the conductive pads are electrically connected to the corresponding conductive through holes, thereby dispensing with the conventional wet etching process and hence preventing an undercut structure from being formed under the conductive pads.

Abstract translation: 提供了一种用于制造插入件的方法，其包括以下步骤：提供具有相对的第一和第二侧面的基板本体和连通第一和第二侧面的多个导电通孔; 在所述基板主体的第一侧上形成绝缘层，其中所述绝缘层具有多个对应地暴露所述导电通孔的开口; 并且在绝缘层的开口中形成多个导电焊盘，其中导电焊盘电连接到相应的导电通孔，从而分配常规的湿蚀刻工艺，从而防止在导电焊盘下方形成底切结构 。

公开(公告)号：US08970038B2

公开(公告)日：2015-03-03

申请号：US13677939

申请日：2012-11-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Hung Lu ,  Chung-Te Yuan ,  Guang-Hwa Ma

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/73204

Abstract: A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate.

Abstract translation: 提供一种半导体衬底，包括：衬底; 多个导电通孔嵌入基板中; 形成在所述基板上的第一电介质层; 形成在所述第一电介质层上的金属层; 以及形成在所述金属层上的第二电介质层。 因此，当包装基板设置在第二电介质层上时，金属层提供反向应力以平衡由第一和第二电介质层引起的热应力，从而防止半导体衬底翘曲。

公开(公告)号：US20140217605A1

公开(公告)日：2014-08-07

申请号：US13894687

申请日：2013-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Hung Lin ,  Chun-Hung Lu ,  Guang-Hwa Ma ,  Hsiao-Chun Huang ,  Kuang-Hsin Chen

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76802 ,  H01L21/76808 ,  H01L23/49894 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

Abstract translation: 公开了一种用于封装的互连结构。 互连结构包括在其表面上形成有导电部分的基板主体; 形成在所述基板主体的表面上并且具有用于使所述导电部暴露的通孔的第一光敏介电层; 在通孔中形成的导电通孔; 形成在所述第一光敏介电层上并具有用于使所述导电通孔和所述第一光敏介电层的一部分暴露的开口的第二光敏介电层; 以及形成在第二感光介电层的开口中的导电迹线层，以便通过导电通孔电连接到导电部分，从而简化制造工艺并降低制造成本和时间。

公开(公告)号：US09903024B2

公开(公告)日：2018-02-27

申请号：US14688510

申请日：2015-04-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Yi Wu ,  Chun-Hung Lu

IPC: H05K1/11 ,  C23F1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14

CPC classification number: C23F1/00 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

公开(公告)号：US20170148761A1

公开(公告)日：2017-05-25

申请号：US15400608

申请日：2017-01-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

公开(公告)号：US09515048B2

公开(公告)日：2016-12-06

申请号：US14744464

申请日：2015-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Kuang Wu ,  Tsung-Te Yuan ,  Chun-Hung Lu

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/522

CPC classification number: H01L24/97 ,  H01L21/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2924/00

Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having a chip mounting side and an opposite external connection side and a plurality of conductive through holes communicating the chip mounting side and the external connection side, wherein the chip mounting side of the substrate body is covered with a protection layer; performing a singulation process on the external connection side of the substrate body; bonding the substrate body to a carrier via the external connection side thereof; removing the protection layer; and removing the carrier to form a plurality of interposers, thereby simplifying the fabrication process and improving the product yield.

Abstract translation: 提供了一种制造插入件的方法，其包括以下步骤：提供具有芯片安装侧和相对的外部连接侧的基板主体和连接芯片安装侧和外部连接侧的多个导电通孔，其中， 衬底主体的芯片安装侧被保护层覆盖; 在所述基板主体的外部连接侧进行切割处理; 通过其外部连接侧将衬底本体连接到载体上; 去除保护层; 并移除载体以形成多个插入物，从而简化制造工艺并提高产品产率。

公开(公告)号：US20160141255A1

公开(公告)日：2016-05-19

申请号：US14824570

申请日：2015-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/54 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

Abstract translation: 提供了一种半导体封装，其包括：具有第一底表面和与第一底表面相对的第一顶表面的电路结构; 至少一个半导体元件，设置在电路结构的第一顶表面上并电连接到电路结构; 形成在所述电路结构的第一顶表面上以封装所述半导体元件的密封剂，其中所述密封剂具有面向所述电路结构的第一顶表面的第二底表面和与所述第二底表面相对的第二顶表面; 以及形成在密封剂的第二顶表面上或形成在电路结构和密封剂之间或形成在电路结构的第一底表面上的强化层，从而有效地防止密封剂翘曲并且半导体元件破裂。