公开(公告)号：US5674355A

公开(公告)日：1997-10-07

申请号：US483682

申请日：1995-06-07

申请人： Stephan Alan Cohen ,  Daniel Charles Edelstein ,  Alfred Grill ,  Jurij Rostyslav Paraszczak ,  Vishnubhai Vitthalbhai Patel

发明人： Stephan Alan Cohen ,  Daniel Charles Edelstein ,  Alfred Grill ,  Jurij Rostyslav Paraszczak ,  Vishnubhai Vitthalbhai Patel

IPC分类号： H01L21/8238 ,  H01L21/314 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L21/306

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02274 ,  H01L23/5329 ,  H01L2924/0002

摘要： The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon as an insulator for spacing apart one or more levels of a conductor on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer from a substrate containing such a layer.

公开(公告)号：US5679269A

公开(公告)日：1997-10-21

申请号：US631239

申请日：1996-04-12

申请人： Stephan Alan Cohen ,  Daniel Charles Edelstein ,  Alfred Grill ,  Jurij Rostyslav Paraszczak ,  Vishnubhai Vitthalbhai Patel

发明人： Stephan Alan Cohen ,  Daniel Charles Edelstein ,  Alfred Grill ,  Jurij Rostyslav Paraszczak ,  Vishnubhai Vitthalbhai Patel

IPC分类号： H01L21/8238 ,  H01L21/314 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L21/00 ,  H01L31/0312

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02274 ,  H01L23/5329 ,  H01L2924/0002

摘要： The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon as an insulator for spacing apart one or more levels of a conductor on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer from a substrate containing such a layer.

摘要翻译： 本发明涉及半导体器件，其包括作为其结构元件之一的类金刚石碳作为绝缘体，用于将集成电路芯片上的一个或多个级别的导体间隔开。 本发明还涉及一种形成一体结构的方法及其制造的一体结构。 本发明还提供了一种用于从含有这种层的衬底选择性地离子蚀刻类金刚石碳层的方法。

公开(公告)号：US07276787B2

公开(公告)日：2007-10-02

申请号：US10729254

申请日：2003-12-05

申请人： Daniel Charles Edelstein ,  Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Jon Alfred Casey ,  Sherif A. Goma ,  Raymond R. Horton ,  Gareth Geoffrey Hougham ,  Michael Wayne Lane ,  Xiao Hu Liu ,  Chirag Suryakant Patel ,  Edmund Juris Sprogis ,  Michelle Leigh Steen ,  Brian Richard Sundlof ,  Cornelia K. Tsang ,  George Frederick Walker

发明人： Daniel Charles Edelstein ,  Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Jon Alfred Casey ,  Sherif A. Goma ,  Raymond R. Horton ,  Gareth Geoffrey Hougham ,  Michael Wayne Lane ,  Xiao Hu Liu ,  Chirag Suryakant Patel ,  Edmund Juris Sprogis ,  Michelle Leigh Steen ,  Brian Richard Sundlof ,  Cornelia K. Tsang ,  George Frederick Walker

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/4763 ,  H01L29/40 ,  H01L23/52

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US06646345B2

公开(公告)日：2003-11-11

申请号：US09966629

申请日：2001-09-27

申请人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

发明人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

IPC分类号： H01L2348

CPC分类号： H01L21/76846 ,  C23C18/1651 ,  C23C18/1841 ,  C23C18/44 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76874 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.

公开(公告)号：US06399496B1

公开(公告)日：2002-06-04

申请号：US09714504

申请日：2000-11-16

申请人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

发明人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

摘要翻译： 本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和 用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。 本发明还公开了用于形成互连结构的方法，该互连结构用于通过首先在电子器件上沉积铜合金或不含铜的其它金属的种子层，然后在其上形成铜导体，从而提供与电子器件的电连接 种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

公开(公告)号：US06291885B1

公开(公告)日：2001-09-18

申请号：US08896925

申请日：1997-07-18

申请人： Cyril Cabral, Jr. ,  Patrick William DeHaven ,  Daniel Charles Edelstein ,  David Peter Klaus ,  James Manley Pollard, III ,  Carol L. Stanis ,  Cyprian Emeka Uzoh

发明人： Cyril Cabral, Jr. ,  Patrick William DeHaven ,  Daniel Charles Edelstein ,  David Peter Klaus ,  James Manley Pollard, III ,  Carol L. Stanis ,  Cyprian Emeka Uzoh

IPC分类号： H01L2348

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/12 ,  H01L29/4933 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

摘要翻译： 描述了用于电互连的互连结构和阻挡层，其结合了诸如Cu的第一材料和诸如Al，W和PbSn的第二材料之间的六方相中的TaN层。 六方相中的TaN多层和α相中的Ta也被描述为阻挡层。 本发明克服了在500℃的温度退火期间将Cu扩散到期望分离的材料中的问题。

公开(公告)号：US6114937A

公开(公告)日：2000-09-05

申请号：US949316

申请日：1997-10-14

申请人： Joachim Norbert Burghartz ,  Daniel Charles Edelstein ,  Christopher Vincent Jahnes ,  Cyprian Emeka Uzoh

发明人： Joachim Norbert Burghartz ,  Daniel Charles Edelstein ,  Christopher Vincent Jahnes ,  Cyprian Emeka Uzoh

IPC分类号： H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F30/16 ,  H01F41/04 ,  H01L23/522 ,  H01F5/00

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F17/0033 ,  H01F27/2804 ,  H01F27/2895 ,  H01F30/16 ,  H01F41/042 ,  H01F41/046 ,  H01F17/06 ,  H01L2924/0002 ,  Y10T29/4902

摘要： High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral metal coil deposited in a trench formed in a dielectric layer over a substrate. The metal coil is enclosed in ferromagnetic liner and cap layers, and is connected to an underpass contact through a metal filled via in the dielectric layer. The spiral inductor also includes ferromagnetic cores lines surrounded by the metal spiral coil. A spiral transformer is formed by vertically stacking two spiral inductors, or placing them side-by-side over a ferromagnetic bridge formed below the metal coils and cores lines. The toroidal inductor includes a toroidal metal coil with a core having ferromagnetic strips. The toroidal metal coil is segmented into two coils each having a pair of ports to form a toroidal transformer.

摘要翻译： 公开了与硅非常大规模集成（VLSI）处理兼容的高质量因子（Q）螺旋和环形电感器和变压器，消耗小的IC区域并在高频下操作。 螺旋电感器具有沉积在形成在衬底上的电介质层中的沟槽中的螺旋金属线圈。 金属线圈封装在铁磁衬垫和盖层中，并通过电介质层中的金属填充通孔连接到地下通道接触。 螺旋电感器还包括由金属螺旋线圈包围的铁磁芯线。 通过垂直堆叠两个螺旋电感器或将它们并排放置在形成在金属线圈和芯线下方的铁磁桥上，形成螺旋形变压器。 环形电感器包括具有铁磁条的芯的环形金属线圈。 环形金属线圈被分成两个线圈，每个线圈具有一对端口以形成环形变压器。

公开(公告)号：US6063651A

公开(公告)日：2000-05-16

申请号：US18145

申请日：1998-02-03

申请人： Daniel Charles Edelstein ,  Chandrasekhar Narayan

发明人： Daniel Charles Edelstein ,  Chandrasekhar Narayan

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： A method and apparatus for activating fusible links on a circuit substrate. The circuit substrate is supported in a fixture which is cooled to a below ambient temperature. Cooling of the circuit substrate decreases the absorption of energy by the substrate, permitting a smaller spot size laser beam having a lower wavelength to be employed for interrupting the fusible links. The substrate is cooled by a refrigeration coil in heat transfer with the fixture holding the substrate. Moisture formation is avoided by placing the substrate and laser source in a controlled atmosphere.

摘要翻译： 一种用于激活电路基板上的可熔链节的方法和装置。 电路基板被支撑在被冷却到低于环境温度的固定装置中。 电路基板的冷却减少了基板的能量吸收，允许采用较低波长的较小的点尺寸的激光束来中断熔丝。 基板通过热传递的冷冻盘管冷却，夹具固定基板。 通过将基板和激光源放置在受控的气氛中来避免水分形成。

公开(公告)号：US06548901B1

公开(公告)日：2003-04-15

申请号：US09596750

申请日：2000-06-15

申请人： William Cote ,  Timothy Joseph Dalton ,  Daniel Charles Edelstein ,  Stephen McConnell Gates

发明人： William Cote ,  Timothy Joseph Dalton ,  Daniel Charles Edelstein ,  Stephen McConnell Gates

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L21/768 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure having reduced fringing fields of bottom corners of said interconnect structure and a method of fabricating the same is provided. The interconnect structure includes one or more interconnect levels one on top of each other, wherein each interconnect level is separated by a diffusion barrier and includes a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, each interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric. The interconnect structures may be fabricated such that top horizontal portions of the metallic lines are coplanar with a top surface of the low-k interlayer dielectric.

摘要翻译： 提供具有减小所述互连结构的底角的边缘的互连结构及其制造方法。 互连结构包括彼此之上的一个或多个互连层，其中每个互连层由扩散阻挡隔开，并且包括在至少一个混合电介质上的至少一个低k​​层间电介质的电介质叠层，所述电介质具有 每个互连层还包括形成在所述低k层间电介质中的金属线，条件是所述金属线的底部水平部分与所述界面不一致，并且所述金属线包含在所述低k层间电介质中 电介质。 可以制造互连结构，使得金属线的顶部水平部分与低k层间电介质的顶表面共面。

公开(公告)号：US06486557B1

公开(公告)日：2002-11-26

申请号：US09515110

申请日：2000-02-29

申请人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

发明人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.

摘要翻译： 集成电路芯片上的多层共面铜镶嵌互连结构包括在集成电路基板上的第一平面互连层，并且具有由具有相对较低的介电常数和相对低的弹性模量的介电材料隔开的多个线导体。 第一平面互连层上的第二平面互连层包括具有高于第一平面互连层的弹性模量和通过其的导电通孔的电介质膜。 通孔选择性地与线路导体接触。 第二平面互连层上的第三平面互连层具有被电介质材料隔开并选择性地与通孔接触的多个线导体。