公开(公告)号：US12119281B2

公开(公告)日：2024-10-15

申请号：US17394093

申请日：2021-08-04

申请人： Qorvo US, Inc.

发明人： Dylan Murdock

IPC分类号： H01L23/31 ,  H01L23/04 ,  H01L23/10 ,  H01L23/29 ,  H01L23/00 ,  H01L23/373

CPC分类号： H01L23/3142 ,  H01L23/04 ,  H01L23/10 ,  H01L23/291 ,  H01L23/315 ,  H01L23/3736 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48225 ,  H01L2224/49176 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01403 ,  H01L2924/05432 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/173 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/3512

摘要： The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

公开(公告)号：US20240332117A1

公开(公告)日：2024-10-03

申请号：US18295217

申请日：2023-04-03

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Changsun Yun ,  Oseob JEON

IPC分类号： H01L23/367 ,  H01L23/04 ,  H01L23/42

CPC分类号： H01L23/3675 ,  H01L23/041 ,  H01L23/42 ,  H01L23/315

摘要： An injectable conductive component can be used to couple a high-power semiconductor chip assembly to a heat sink, in automotive and industrial applications. The injectable conductive component provides a low-resistance interface material and also acts as a bonding agent. A cavity bounded by the chip assembly and the heat sink can form a container for the injectable conductive component, which remains in a liquid phase during operation of the chip assembly. The container can be formed as a cavity by either removing a portion of the heat sink, or by introducing a spacer between the chip assembly and the heat sink, using a sealing material. The injectable conductive component can be introduced into the cavity by injection through a hole formed in a back side of the heat sink.

公开(公告)号：US12087729B2

公开(公告)日：2024-09-10

申请号：US17406097

申请日：2021-08-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Yuan Chang

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/20 ,  H01L23/24 ,  H01L23/31 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L21/56 ,  H01L23/20 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/315 ,  H01L25/50 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181

摘要： A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.

公开(公告)号：US12080625B2

公开(公告)日：2024-09-03

申请号：US18235668

申请日：2023-08-18

申请人： Infineon Technologies Austria AG

发明人： Li Fong Chong ,  Yee Beng Daryl Yeow ,  Chii Shang Hong ,  Azlina Kassim ,  Hui Kin Lit

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/433

CPC分类号： H01L23/4334 ,  H01L21/561 ,  H01L21/565 ,  H01L23/315 ,  H01L23/49503 ,  H01L23/562 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48245

摘要： A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.

公开(公告)号：US20240266244A1

公开(公告)日：2024-08-08

申请号：US18394562

申请日：2023-12-22

申请人： Zhuhai ACCESS Semiconductor Co., LTD.

发明人： Xianming Chen ,  Xiaowei Xu ,  GAO HUANG ,  Benxia Huang ,  WENJIAN LIN

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/3672 ,  H01L21/4857 ,  H01L23/315 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/182 ,  H01L2924/351

摘要： An embedded and packaged heat dissipation structure and a manufacturing method therefor, and a semiconductor are disclosed. The method includes: forming a first semi-finished plate; forming a heat dissipation plate based on the first metal layer; manufacturing a heat dissipation copper column on the heat dissipation plate; providing a dielectric layer; laminating a second metal layer on the dielectric layer; partially etching the second metal layer and the dielectric layer to form a microchannel; manufacturing a thin metal layer to enable an inner wall of the microchannel to form an isolation layer with an integrated structure to obtain a second semi-finished plate; manufacturing a first cover layer; and laminating the first cover layer and the second semi-finished plate to connect the first cover layer and the isolation layer in a sealed manner to obtain the embedded and packaged heat dissipation structure.

公开(公告)号：US20240203812A1

公开(公告)日：2024-06-20

申请号：US18067375

申请日：2022-12-16

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Takamichi HOSOKAWA ,  Kazuhiro MITAMURA ,  Fumio MURAKAMI ,  Yuji KAYASHIMA ,  Yoshihiro MASUMURA

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/315 ,  H01L23/295 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/30205 ,  H01L2924/37001

摘要： A semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, a plurality of lead portions, and a sealing portion sealing them. The sealing portion has a first main surface and a second main surface opposite the first main surface. A groove portion is formed in the sealing portion at the first main surface. At the first main surface of the sealing portion, each of the first chip mounting portion and the second chip mounting portion is exposed from the sealing portion. At the first main surface of the sealing portion, the groove portion is formed between an exposed portion of the first chip mounting portion and an exposed portion of the second chip mounting portion.

公开(公告)号：US11984408B2

公开(公告)日：2024-05-14

申请号：US17453202

申请日：2021-11-02

申请人： NXP USA, Inc.

发明人： You Ge ,  Zhijie Wang ,  Yit Meng Lee ,  Mariano Layson Ching, Jr.

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/562 ,  H01L21/565 ,  H01L23/315 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L2924/181

摘要： A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

公开(公告)号：US20240014188A1

公开(公告)日：2024-01-11

申请号：US17951722

申请日：2022-09-23

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Xiaofei SUN ,  Changhao QUAN

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L25/105 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/16 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/315 ,  H01L21/565 ,  H01L21/4857 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1436 ,  H01L2924/3025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/16227 ,  H01L2224/73265 ,  H01L2224/73215

摘要： A semiconductor package assembly and manufacturing method are provided. The assembly includes: a base plate having a first surface; a chip stacking structure located on the base plate, the chip stacking structure including multiple chips sequently stacked in a direction perpendicular to the base plate and being electrically connected to the first surface; an interposer located on the chip stacking structure and having a first interconnection surface, the first interconnection surface having first and second interconnection regions, and the first interconnection region being electrically connected to the base plate; and a molding compound sealing the chip stacking structure, interposer and first surface. The first interconnection region is not sealed by the molding compound and the second interconnection region is sealed by the compound. There is a preset height between a top surface of the molding compound on the second interconnection region and the first interconnection region.

公开(公告)号：US11854837B2

公开(公告)日：2023-12-26

申请号：US17346972

申请日：2021-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Chien-Sheng Chen ,  Shin-Puu Jeng

IPC分类号： H01L21/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L21/56 ,  H01L23/315

摘要： Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

公开(公告)号：US20230386863A1

公开(公告)日：2023-11-30

申请号：US18447443

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Chien-Sheng Chen ,  Shin-Puu Jeng

IPC分类号： H01L21/56 ,  H01L23/31

CPC分类号： H01L21/56 ,  H01L23/315

摘要： Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.