公开(公告)号：US20240363444A1

公开(公告)日：2024-10-31

申请号：US18770299

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0623 ,  H01L27/0886 ,  H01L27/1207 ,  H01L27/1211

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.

公开(公告)号：US20240363429A1

公开(公告)日：2024-10-31

申请号：US18771662

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

Abstract: A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.

公开(公告)号：US20240363423A1

公开(公告)日：2024-10-31

申请号：US18767533

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yao WU ,  Chang-Yun Chang ,  Ming-Chang Wen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/401

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.

公开(公告)号：US12132111B2

公开(公告)日：2024-10-29

申请号：US16936921

申请日：2020-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen Yang ,  Tsung-Yu Chiang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/4916 ,  H01L29/66795

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first gate stack and the second gate stack. The method also includes forming a protection element to cover the second gate stack. The method further includes replacing the first gate stack with a metal gate stack after the formation of the protection element.

公开(公告)号：US12132100B2

公开(公告)日：2024-10-29

申请号：US18186567

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L25/18 ,  H01L27/088 ,  H10B10/00

CPC classification number: H01L29/66795 ,  H01L21/02008 ,  H01L21/02532 ,  H01L21/823431 ,  H01L25/18 ,  H01L27/0886 ,  H10B10/12

Abstract: A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.

公开(公告)号：US12132050B2

公开(公告)日：2024-10-29

申请号：US18526062

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L27/0886 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7842 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/3212

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US20240357804A1

公开(公告)日：2024-10-24

申请号：US18757580

申请日：2024-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H10B20/20 ,  G06F12/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00

CPC classification number: H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

Abstract: A memory device includes: a substrate; a semiconductor fin over the substrate in a first direction; a first gate electrode and a second gate electrode over the substrate in a second direction, the semiconductor fin extending through the second gate electrode and terminating at the first gate electrode; a first gate dielectric layer arranged between the semiconductor fin and the first gate electrode; and a second gate dielectric layer arranged between the semiconductor fin and the second gate electrode. The second gate electrode is configured as a read transistor of a first memory cell, in which the second gate dielectric layer is kept intact, and the first gate electrode is configured as a program transistor of the first memory cell, in which an occurrence or an absence of an electrical breakdown in the first gate dielectric layer represents a binary logic state of the first memory cell.

公开(公告)号：US20240355896A1

公开(公告)日：2024-10-24

申请号：US18760602

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US20240355819A1

公开(公告)日：2024-10-24

申请号：US18760970

申请日：2024-07-01

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L29/0669 ,  H01L29/785 ,  H01L2029/7858

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20240347618A1

公开(公告)日：2024-10-17

申请号：US18755189

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Christine RADLINGER ,  Tongtawee WACHARASINDHU ,  Andre BARAN ,  Kiran CHIKKADI ,  Devin MERRILL ,  Nilesh DENDGE ,  David J. TOWNER ,  Christopher KENYON

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/517 ,  H01L27/0886 ,  H01L29/42364

Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.