公开(公告)号：US20240363457A1

公开(公告)日：2024-10-31

申请号：US18767481

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Hung Chen ,  Hong-Seng Shue ,  Po-Hao Tsai ,  Mirng-Ji Lii

IPC分类号： H01L23/10 ,  H01L21/50 ,  H01L21/762 ,  H01L23/522

CPC分类号： H01L23/10 ,  H01L21/50 ,  H01L21/76297 ,  H01L23/5226

摘要： A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

公开(公告)号：US12132050B2

公开(公告)日：2024-10-29

申请号：US18526062

申请日：2023-12-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC分类号： H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/321

CPC分类号： H01L27/0886 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7842 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/3212

摘要： Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US20240355903A1

公开(公告)日：2024-10-24

申请号：US18763777

申请日：2024-07-03

申请人： Intel Corporation

发明人： Biswajeet GUHA ,  Dax M. CRUM ,  Stephen M. CEA ,  Leonard P. GULER ,  Tahir GHANI

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7853

摘要： Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

公开(公告)号：US20240355896A1

公开(公告)日：2024-10-24

申请号：US18760602

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

摘要： A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US20240355618A1

公开(公告)日：2024-10-24

申请号：US18761373

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Ta Wu ,  Chia-Ta Hsieh ,  Kuo Wei Wu ,  Yu-Chun Chang ,  Ying Ling Tseng

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L21/02359 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649

摘要： Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

公开(公告)号：US12125923B2

公开(公告)日：2024-10-22

申请号：US17191173

申请日：2021-03-03

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jaroslav Pjencak ,  Moshe Agam ,  Johan Camiel Julia Janssens

IPC分类号： H01L29/861 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/861 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/76291 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/6609 ,  H01L29/7824

摘要： A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.

公开(公告)号：US20240347571A1

公开(公告)日：2024-10-17

申请号：US18756313

申请日：2024-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Yung-Hsiang CHEN ,  Yu-Lung YEH ,  Yen-Hsiu CHEN ,  Bo-Chang SU ,  Cheng-Hsien CHEN

IPC分类号： H01L27/146 ,  H01L21/762

CPC分类号： H01L27/1463 ,  H01L21/76224 ,  H01L27/14623 ,  H01L27/14685 ,  H01L27/14627

摘要： A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.

公开(公告)号：US20240347377A1

公开(公告)日：2024-10-17

申请号：US18754653

申请日：2024-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Pu-Fang Chen ,  Cheng-Ta Wu ,  Po-Jung Chiang ,  Ru-Liang Lee ,  Victor Y. Lu ,  Yen-Hsiu Chen ,  Yeur-Luen Tu ,  Yu-Lung Yeh ,  Shi-Chieh Lin

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/84

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/84 ,  H01L21/26506

摘要： Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

公开(公告)号：US20240347375A1

公开(公告)日：2024-10-17

申请号：US18135350

申请日：2023-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： KUO-CHUNG HSU ,  EN-JUI LI

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H10B10/00 ,  H10B12/00 ,  H10B20/25

摘要： A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate having an active region and a shallow trench isolation (STI) adjacent to the active region of the substrate. The STI includes a charge trapping layer and a liner disposed between the charge trapping layer and the active region of the substrate, wherein the charge trapping layer is doped with an impurity.

公开(公告)号：US12119267B2

公开(公告)日：2024-10-15

申请号：US18151412

申请日：2023-01-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chen-Cheng Chou ,  Shiu-Ko Jangjian ,  Cheng-Ta Wu

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/02164 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/3247 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886

摘要： A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.