公开(公告)号：US11823757B2

公开(公告)日：2023-11-21

申请号：US17000130

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0897 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G06F2212/205 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C2029/3202 ,  Y02D10/00

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

公开(公告)号：US11823734B2

公开(公告)日：2023-11-21

申请号：US17295753

申请日：2019-11-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/14 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4085 ,  G11C2207/002 ,  G11C2207/005

Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.

公开(公告)号：US20230362041A1

公开(公告)日：2023-11-09

申请号：US18142977

申请日：2023-05-03

Applicant: Rambus Inc.

Inventor： Ehud Nir

IPC: H04L25/03 ,  H04L27/06

CPC classification number: H04L25/03057 ,  H04L27/06 ,  H04L25/4917

Abstract: Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.

公开(公告)号：US20230360694A1

公开(公告)日：2023-11-09

申请号：US18195877

申请日：2023-05-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406

CPC classification number: G11C11/4093 ,  G11C11/4096 ,  G11C5/025 ,  G11C5/04 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  G11C5/02 ,  H01L23/481 ,  G11C11/406 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L24/73

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20230359572A1

公开(公告)日：2023-11-09

申请号：US18135095

申请日：2023-04-14

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G11C7/22 ,  G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/222 ,  G11C7/04

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US11803489B2

公开(公告)日：2023-10-31

申请号：US17849450

申请日：2022-06-24

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20230342310A1

公开(公告)日：2023-10-26

申请号：US18025571

申请日：2021-08-30

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Thomas Vogelsang

IPC: G06F13/16 ,  G06N3/048 ,  G06N3/084

CPC classification number: G06F13/1668 ,  G06N3/048 ,  G06N3/084 ,  G06F2213/16

Abstract: An application-specific integrated circuit for an artificial neural network is integrated with a high-bandwidth memory. A processing die with tiled neural-network processing units is bonded to a stack of memory dies with memory banks laid out to establish relatively short connections to overlying processing units. The memory banks form vertical groups of banks for each overlying processing unit. A switch matrix on the processing die allows each processing unit to communicate with its vertical group of banks via a short, fast inter-die memory channel or with more remote groups of banks under neighboring processing units.

公开(公告)号：US20230333927A1

公开(公告)日：2023-10-19

申请号：US18095341

申请日：2023-01-10

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

公开(公告)号：US20230325309A1

公开(公告)日：2023-10-12

申请号：US18210387

申请日：2023-06-15

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G11C7/22 ,  G11C8/10 ,  G11C7/1006 ,  G11C7/1039 ,  H05K999/99 ,  G11C2207/107 ,  G06F2212/2024

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US11782788B2

公开(公告)日：2023-10-10

申请号：US17585654

申请日：2022-01-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C29/00 ,  G06F12/0882 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0882 ,  G06F2212/7201

Abstract: A hybrid volatile/non-volatile memory employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). The memory supports error-detection and correction (EDC) techniques by allocating a fraction of DRAM storage to information calculated for each unit of stored data that can be used to detect and correct errors. An interface between the DRAM cache and NVM executes a wear-leveling scheme that aggregates and distributes NVM data and EDC write operations in a manner that prolongs service life.