公开(公告)号：US20160173036A1

公开(公告)日：2016-06-16

申请号：US14955969

申请日：2015-12-01

Applicant: STMicroelectronics SA

Inventor： Lionel Vogt ,  Baudouin Martineau ,  Aurelien Larie

IPC: H03F1/02 ,  H03F3/193 ,  H03F3/21

CPC classification number: H03F1/0205 ,  H03F1/0261 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45179 ,  H03F2200/432 ,  H03F2200/451 ,  H03F2200/516 ,  H03F2203/21106 ,  H03F2203/45394

Abstract: An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.

Abstract translation: 放大器包括并联耦合的至少两个放大级。 每个放大级包括在具有连接到放大级共同的第一和第二输入节点的栅极的差分对放大MOS晶体管和彼此连接但与其它放大级的放大MOS晶体管的体区绝缘的体区域。 配置电路产生用于施加到每个放大级中的批量端子的偏压，以设置放大MOS晶体管的阈值电压，从而构成每个放大级的工作范围，使得不同的放大级具有不同的工作范围。

公开(公告)号：US09368611B2

公开(公告)日：2016-06-14

申请号：US13853111

申请日：2013-03-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS S.A.

Inventor： Philippe Galy ,  Patrice Dehan ,  Boris Heitz ,  Jean Jimenez

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/07

CPC classification number: H01L29/78 ,  H01L27/0727 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66643 ,  H01L29/7839

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。

公开(公告)号：US09354391B2

公开(公告)日：2016-05-31

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/12 ,  G02B6/122 ,  H01L25/16 ,  H01L27/02 ,  H01L23/60 ,  H01L25/065 ,  H01L23/00

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。

公开(公告)号：US20160099183A1

公开(公告)日：2016-04-07

申请号：US14965990

申请日：2015-12-11

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Richard ,  Francois Andrieu

IPC: H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603

Abstract: The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor.

公开(公告)号：US09305828B2

公开(公告)日：2016-04-05

申请号：US14526005

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Emmanuel Josse ,  Olivier Nier

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/324 ,  H01L21/76237 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7847

Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.

Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。

公开(公告)号：US20160093662A1

公开(公告)日：2016-03-31

申请号：US14953973

申请日：2015-11-30

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Laurent Frey

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/035236 ,  H01L31/107

Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.

公开(公告)号：US09299668B2

公开(公告)日：2016-03-29

申请号：US13705503

申请日：2012-12-05

Applicant: STMicroelectronics S.A.

Inventor： Johan Bourgeat ,  Philippe Galy

IPC: H02H9/00 ,  H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L27/0274 ,  H01L27/0296 ,  H01L29/0692 ,  H01L29/747 ,  H01L2924/0002 ,  H02H9/04 ,  H01L2924/00

Abstract: A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.

Abstract translation: 用于保护一组N个节点免受静电放电的装置，其中N大于或等于3，包括分别具有分别连接到N个节点的N个第一终端的N个单元的集合和连接在一起的N个第二终端以形成公共 终奌站。 每个单元包括至少一个MOS晶体管，其包括连接在一对N个节点之间的寄生晶体管，并且在所述一对节点之间存在电流脉冲的情况下，配置为至少临时地以包括MOS- 在亚阈值模式下工作和双极晶体管的工作。

公开(公告)号：US09298666B2

公开(公告)日：2016-03-29

申请号：US13300318

申请日：2011-11-18

Applicant: Stéphane Le Tual ,  Pratap Singh

Inventor： Stéphane Le Tual ,  Pratap Singh

IPC: H04L7/00 ,  G06F13/42

CPC classification number: G06F13/423

Abstract: The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

Abstract translation: 本发明涉及一种电路，包括：适于接收第一时钟信号（CLK1）并在由所述第一时钟信号确定的时间提供第一输出数据信号的第一电路块（302） 适于接收第二时钟信号（CLK2）并在由所述第二时钟信号确定的时间提供第二输出数据信号的第二电路块（304） 连接到所述第一和第二电路块的相应输出的时钟总线（314），用于基于所述第一和第二时钟信号接收第三时钟信号（BCLK）; 以及耦合到所述时钟总线并适于基于所述第三时钟信号对所述第一和第二输出数据信号进行采样的同步单元（312）。

公开(公告)号：US20160056612A1

公开(公告)日：2016-02-25

申请号：US14827429

申请日：2015-08-17

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/343

CPC classification number: H01S5/1237 ,  G02B6/30 ,  G02B6/34 ,  G02B2006/12061 ,  G02B2006/12121 ,  H01L2224/32 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/0421 ,  H01S5/1014 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/187 ,  H01S5/323 ,  H01S5/343 ,  H01S2301/166

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising:a III-V heterostructure gain medium (3); andan optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon.The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

Abstract translation: 本发明涉及一种布置在硅中和/或硅上的III-V异质结构激光器件，包括：III-V异质结构增益介质; 以及面向所述增益介质（3）布置并包括配备有纵向肋（17）的平板波导（15）的光学肋波导（11），所述光学波纹管（11）布置在所述硅中。 光学肋波导（11）被定向成使得至少一个布拉格光栅（19,19a，19b）布置在相对于增益介质（3）近端的平板波导（15）的该侧（21）上， 因为肋（17）被放置在相对于增益介质（3）远端的平板波导（15）的该侧（23）上。

公开(公告)号：US09268743B2

公开(公告)日：2016-02-23

申请号：US13949884

申请日：2013-07-24

Applicant: STMicroelectronics SA

Inventor： Jean-Robert Manouvrier

IPC: G06F17/50 ,  G06F17/10

CPC classification number: G06F17/10 ,  G06F17/5036

Abstract: The electric behavior of a reverse-biased PN junction diode is modeled by measuring the value of voltage V present across the diode and the value of the corresponding current I running through this diode, the voltage V varying within a range of values including the value of diode breakdown voltage. A representation of a function ln ⁡ ( I - I s ) according to voltage V is established from the measured values of current I and of voltage V, IS being the saturation current of the diode. A linear function representative of a substantially linear portion of the function, characterized by voltages V greater than breakdown voltage VBK in terms of absolute value, is determined. An avalanche multiplication factor MM is then calculated by MM = 1 + ⅇ ( - slbv · V + bv bv ) , with parameter slbv equal to the ordinate at the origin of the linear function, and parameter slbv/bv equal to the slope of the linear function.

Abstract translation: 反向偏置PN结二极管的电气行为通过测量二极管上存在的电压V的值和通过该二极管的相应电流I的值来建模，电压V在包括的值的范围内变化 二极管击穿电压。 根据电压I和电压V的测量值建立函数ln⁡（I-I s）的表示，IS是二极管的饱和电流。 确定表示功能的基本线性部分的线性函数，其特征在于以绝对值计的大于击穿电压VBK的电压V。 然后通过MM = 1 +ⅇ（ - slbv·V + bv bv）计算雪崩倍增因子MM，参数slbv等于线性函数原点的纵坐标，参数slbv / bv等于 线性函数。