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    CHIP STRUCTURE AND MULTI-CHIP STACK PACKAGE
    91.
    发明申请
    CHIP STRUCTURE AND MULTI-CHIP STACK PACKAGE 有权
    芯片结构和多芯片堆叠包装

    公开(公告)号：US20140159253A1

    公开(公告)日：2014-06-12

    申请号：US13845129

    申请日：2013-03-18

    申请人： CHIPMOS TECHNOLOGIES INC.

    发明人： Tsung-Jen Liao

    IPC分类号： H01L23/538

    CPC分类号： H01L23/5386 ,  H01L23/481 ,  H01L24/11 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L2224/16145 ,  H01L2224/49174 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/00

    摘要： A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces respectively connected to the active surface and the back surface. The chip includes at least one bond pad disposed on the active surface and at least one joint pad disposed on the back surface. The interlink plate substantially parallel to one of the side surfaces includes a base and a conductive pattern disposed on the base. The conductive pattern is located between the base and the chip. The first connection terminals are disposed between the chip and the interlink plate. The bond pad is electrically connected to the joint pad through the first connection terminals and the conductive pattern.

    摘要翻译： 提供了芯片结构和多芯片堆叠封装。 芯片结构包括芯片，至少一个互连板和多个第一连接端子。 芯片具有活性表面，与活性表面相对的后表面和分别连接到活性表面和后表面的多个侧表面。 芯片包括设置在有源表面上的至少一个接合焊盘和设置在后表面上的至少一个接合焊盘。 基本上平行于一个侧表面的互连板包括基部和设置在基部上的导电图案。 导电图案位于基底和芯片之间。 第一连接端子设置在芯片和互连板之间。 接合焊盘通过第一连接端子和导电图案电连接到接头焊盘。

    WAFER LEVEL CHIP SCALE PACKAGE
    93.
    发明申请
    WAFER LEVEL CHIP SCALE PACKAGE 审中-公开
    WAFER LEVEL CHIP SCALE包装

    公开(公告)号：US20140061880A1

    公开(公告)日：2014-03-06

    申请号：US13935911

    申请日：2013-07-05

    申请人： CHIPMOS TECHNOLOGIES INC.

    发明人： TSUNG JEN LIAO

    IPC分类号： H01L21/768 ,  H01L23/538

    CPC分类号： H01L21/76894 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device including a semiconductor element having a first surface and a second surface, which is opposite to the first surface, and a conductive via disposed on the semiconductor element. The semiconductor element includes a die; a first redistribution layer positioned on the first surface, wherein the first redistribution layer is configured to fan out the die; and a second redistribution layer positioned on the second surface of the semiconductor element. The conductive via is configured to electrically connect the first redistribution layer and the second redistribution layer, wherein the sizes of the two ends of the conductive via are different and the die can be electrically coupled to another semiconductor device through the conductive via.

    摘要翻译： 本公开提供了一种半导体器件，其包括具有与第一表面相对的第一表面和第二表面的半导体元件和设置在半导体元件上的导电通孔。 半导体元件包括： 位于所述第一表面上的第一再分配层，其中所述第一再分配层被配置为扇出所述管芯; 以及位于半导体元件的第二表面上的第二再分配层。 导电通孔被配置为电连接第一再分配层和第二再分配层，其中导电通孔的两端的尺寸不同，并且管芯可以通过导电通孔电耦合到另一个半导体器件。

    SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    96.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    半导体封装结构及其制造方法

    公开(公告)号：US20130181333A1

    公开(公告)日：2013-07-18

    申请号：US13655434

    申请日：2012-10-18

    申请人： ChipMOS Technologies Inc.

    发明人： Shih-Wen Chou

    IPC分类号： H01L23/495 ,  H01L21/50

    CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2225/1029 ,  H01L2225/1088 ,  H01L2924/00014

    摘要： A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.

    摘要翻译： 提供一种制造半导体封装结构的方法。 支撑板的上表面上的支撑板和多个衬垫图案限定容纳腔。 在填充图案上形成彼此电绝缘的多个引线，从衬垫图案的顶表面沿着侧表面延伸到上表面并位于容纳腔内。 芯片安装在容纳腔内，电连接到引线。 形成模塑料以至少封装芯片，引线的一部分和支撑板的一部分填充填充图案中的容纳腔和间隙，并且使顶部表面上的一部分引线露出。 移除支撑板以暴露每个填充图案的背面，模制化合物的底表面和每个引线的下表面。

    SEMICONDUCTOR WAFER DESIGNED TO AVOID PROBED MARKS WHILE TESTING
    98.
    发明申请
    SEMICONDUCTOR WAFER DESIGNED TO AVOID PROBED MARKS WHILE TESTING 失效
    SEMICONDUCTOR WAFER设计用于避免检测时发现的标记

    公开(公告)号：US20020180026A1

    公开(公告)日：2002-12-05

    申请号：US09873420

    申请日：2001-06-05

    申请人： ChipMOS TECHNOLOGIES INC.

    发明人： An-Hong Liu ,  Yuan-Ping Tseng

    IPC分类号： H01L023/58

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2224/02166 ,  H01L2224/02377

    摘要： A semiconductor wafer is disclosed for avoiding probed marks while testing. The wafer has a plurality of metal interconnects, each metal interconnect connecting underlying bonding pad, corresponding contact pad and test pad. Each contact pad being outer electrical connection terminal is connected in series by a metal interconnect between test pad and bonding pad, so that the section of the metal interconnect between bonding pad and contact pad enable be tested during probing the test pad. Furthermore, there is no probing mark on the contact pad.

    摘要翻译： 公开了一种用于在测试时避免探测痕迹的半导体晶片。 晶片具有多个金属互连，每个金属互连件连接下面的焊盘，相应的接触焊盘和测试焊盘。 作为外部电连接端子的每个接触焊盘通过测试焊盘和焊盘之间的金属互连串联连接，使得在探测测试焊盘期间可以测试接合焊盘和接触焊盘之间的金属互连部分。 此外，接触垫上没有探测标记。