公开(公告)号：US08945414B1

公开(公告)日：2015-02-03

申请号：US14079442

申请日：2013-11-13

Applicant: Intermolecular Inc.

Inventor： Jingang Su ,  Ashish Bodke ,  Abhijit Pethe ,  J Watanabe

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/02046 ,  H01L22/12 ,  H01L22/26

Abstract: Oxides (e.g., native or thermal silicon oxide) are etched from underlying silicon with a mixture of fluorine and oxygen radicals generated by a remote plasma. The oxygen radicals rapidly oxidize any uncovered bare silicon areas, preventing the pitting that can result from fluorine etching bare silicon more rapidly than it etches the surrounding oxide. A very thin (few Å), highly uniform passivation layer remaining on the silicon after the process may be left in place or removed. An oxygen-impermeable layer may be formed in-situ immediately afterward to prevent further oxidation. A pre-treatment with oxygen radicals alone fills pores and gaps in the oxide before etching begins.

Abstract translation: 通过由远程等离子体产生的氟和氧自由基的混合物从下面的硅蚀刻氧化物（例如天然或热氧化硅）。 氧自由基快速氧化任何未覆盖的裸硅区域，防止氟蚀刻裸硅的点蚀比其蚀刻周围氧化物更快。 在该过程之后残留在硅上的非常薄（几埃）的高度均匀的钝化层可能留在原位或去除。 可以立即就地形成不透氧层，以防止进一步的氧化。 单独的氧自由基的预处理在蚀刻开始之前填充氧化物中的孔隙和间隙。

公开(公告)号：US20150021774A1

公开(公告)日：2015-01-22

申请号：US14507328

申请日：2014-10-06

Applicant: Intermolecular, Inc.

Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

IPC: H01L23/532

CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract translation: 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在有机硅烷包括：炔基，芳基，氟烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基的方法。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

公开(公告)号：US08933429B2

公开(公告)日：2015-01-13

申请号：US13974278

申请日：2013-08-23

Applicant: Intermolecular Inc.

Inventor： Venkat Ananthan ,  Prashant B Phatak

IPC: H01L47/00 ,  H01L45/00 ,  G11C13/00 ,  H01L21/66

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件开关期间的电压降。 选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括设置在两个较高带隙电介质层之间的低带隙电介质层。 高带隙电介质层可以掺杂掺杂材料以在高于存储器件的工作电压的能级下形成阱。

公开(公告)号：US20150010705A1

公开(公告)日：2015-01-08

申请号：US14491407

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L49/02 ,  C23C16/455 ,  H01L29/51 ,  C23C14/22

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US08921151B2

公开(公告)日：2014-12-30

申请号：US13737846

申请日：2013-01-09

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Haifan Liang

IPC: H01L31/18 ,  H01L31/0224 ,  H01L31/0236

CPC classification number: H01L31/18 ,  H01L31/022425 ,  H01L31/02366 ,  Y02E10/50

Abstract: Methods for increasing the power output of a TFPV solar panel using thin absorber layers comprise techniques for roughening and/or texturing the back contact layer. The techniques comprise roughening the substrate prior to the back contact deposition, embedding particles in sol-gel films formed on the substrate, and forming multicomponent, polycrystalline films that result in a roughened surface after a wet etch step, etc.

Abstract translation: 使用薄吸收层增加TFPV太阳能电池板的功率输出的方法包括用于粗糙化和/或纹理化背面接触层的技术。 这些技术包括在后接触沉积之前使基底粗糙化，将颗粒嵌入形成在基底上的溶胶 - 凝胶膜中，以及形成在湿蚀刻步骤之后导致粗糙化表面的多组分多晶膜等。

公开(公告)号：US08913418B2

公开(公告)日：2014-12-16

申请号：US13891472

申请日：2013-05-10

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Vidyut Gopal ,  Chien-Lan Hsueh

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/10 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 可以对包括缺陷源层，缺陷阻挡层和设置在缺陷源层和缺陷阻挡层之间的缺陷受主层的堆叠进行退火。 在退火过程中，缺陷以可控方式从缺陷源层转移到缺陷受体层。 同时，缺陷不会转移到缺陷阻挡层中，从而在缺陷受体层内形成最低浓度区。 该区域负责电阻交换。 精确控制区域的尺寸和区域内的缺陷浓度允许ReRAM单元的电阻开关特性得到显着改善。 在一些实施例中，缺陷源层包括氮氧化铝，缺陷阻挡层包括氮化钛，缺陷受主层包括氧化铝。

公开(公告)号：US20140361236A1

公开(公告)日：2014-12-11

申请号：US14467902

申请日：2014-08-25

Applicant: Intermolecular Inc.

Inventor： Nobumichi Fuchigami ,  Pragati Kumar ,  Prashant B. Phatak

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

Abstract translation: 描述用于形成非易失性电阻式切换存储器的ALD处理技术。 在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成 所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

公开(公告)号：US08907314B2

公开(公告)日：2014-12-09

申请号：US13727958

申请日：2012-12-27

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2− ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x

Abstract translation: 氧化钼可用于在电阻式存储器件中形成开关元件。 氧与钼的原子比可以在2和3之间。氧化钼存在于各种Magneli相中，例如Mo13O33，Mo4O11，Mo17O47，Mo8O23或Mo9O26。 可以跨开关层建立电场，例如通过施加置位或复位电压。 电场可导致氧电荷的移动，例如O 2离子，改变开关层的组成分布，形成双稳态，包括具有MoO 3的高电阻状态和具有MoO x（x <3）的低电阻状态）。

公开(公告)号：US08889492B2

公开(公告)日：2014-11-18

申请号：US14259411

申请日：2014-04-23

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Tony P. Chiang

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

Abstract: Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

公开(公告)号：US08878269B2

公开(公告)日：2014-11-04

申请号：US13738831

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra G. Malhotra ,  Hiroyuki Ode

IPC: H01L27/108

CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。