中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

126 records (took 0.023 seconds)

    Masked sidewall implant for image sensor
    92.
    发明授权
    Masked sidewall implant for image sensor 有权
    用于图像传感器的蒙版侧植入物

    公开(公告)号：US07098067B2

    公开(公告)日：2006-08-29

    申请号：US10905043

    申请日：2004-12-13

    Applicant: James W. Adkisson ,  Mark D. Jaffe ,  Arthur P. Johnson ,  Robert K. Leidy ,  Jeffrey C. Maling

    Inventor： James W. Adkisson ,  Mark D. Jaffe ,  Arthur P. Johnson ,  Robert K. Leidy ,  Jeffrey C. Maling

    IPC: H01L21/00

    CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689

    Abstract: A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.

    Abstract translation: 形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成沟槽隔离区。 该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。 相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。 为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

    Transistor structure with thick recessed source/drain structures and fabrication process of same
    93.
    发明授权
    Transistor structure with thick recessed source/drain structures and fabrication process of same 失效
    晶体管结构具有较厚的凹陷源/漏极结构及其制造工艺

    公开(公告)号：US06870225B2

    公开(公告)日：2005-03-22

    申请号：US09682957

    申请日：2001-11-02

    Applicant: Andres Bryant ,  Mark D. Jaffe

    Inventor： Andres Bryant ,  Mark D. Jaffe

    IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

    CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

    Abstract: An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

    Abstract translation: 一种改进的晶体管结构，可在不增加栅极至S / D电容的情况下降低源/漏（S / D）电阻，从而增加器件工作。 S / D结构通过半导体层形成在半导体晶片上形成的凹槽和具有至少两层的埋入式绝缘体的第一层。 由位于凹部之间的半导体层形成主体，并且主体包括限定主体厚度的顶部主体表面和底部主体表面。 S / D结构的顶部在体厚之内并与之相邻。 还描述了用于形成改进的晶体管结构的改进方法，并且包括：通过半导体层和埋入绝缘体的第一层形成凹槽，使得主体位于凹部之间; 并且将S / D结构形成到凹部中，使得S / D结构的顶部部分在主体厚度之内并且抵接在本体的厚度上。

    Isolation structures for global shutter imager pixel, methods of manufacture and design structures
    98.
    发明授权
    Isolation structures for global shutter imager pixel, methods of manufacture and design structures 有权
    全局快门成像器像素的隔离结构，制造方法和设计结构

    公开(公告)号：US08507962B2

    公开(公告)日：2013-08-13

    申请号：US12897230

    申请日：2010-10-04

    Applicant: Brent A. Anderson ,  Mark D. Jaffe

    Inventor： Brent A. Anderson ,  Mark D. Jaffe

    IPC: H01L31/062

    CPC classification number: H01L27/14603 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14689

    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.

    Abstract translation: 像素传感器单元，例如CMOS光学成像器，制造和设计结构的方法被提供有防止载流子漂移到扩散区域的隔离结构。 像素传感器单元包括感光区域和与感光区域相邻的栅极。 像素传感器单元还包括与栅极相邻的扩散区域。 像素传感器单元还包括位于栅极的沟道区域周围和感光区域下方的隔离区域，其防止在光敏区域中收集的电子漂移到扩散区域。

    SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING
    99.
    发明申请
    SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING 失效
    绝缘子绝缘子基板及其形成方法

    公开(公告)号：US20130196493A1

    公开(公告)日：2013-08-01

    申请号：US13363603

    申请日：2012-02-01

    Applicant: Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

    Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

    IPC: H01L21/265

    CPC classification number: H01L21/76254

    Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

    Abstract translation: 绝缘体上硅（SOI）结构和形成这种结构的相关方法。 在一种情况下，一种方法包括提供绝缘体上硅（SOI）手柄衬底，其具有：沿着手柄衬底的深度的基本均匀的电阻率分布; 和间隙氧（Oi）浓度小于约10ppm（ppma）。 所述方法还包括对所述手柄的表面区域进行反掺杂，使所述表面区域具有大于约3kOhm-cm的电阻率，并且将所述手柄衬底的表面区域与施主晶片接合。

Patent Agency Ranking