公开(公告)号：US07829976B2

公开(公告)日：2010-11-09

申请号：US12419029

申请日：2009-04-06

申请人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

发明人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

摘要翻译： 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US06735855B2

公开(公告)日：2004-05-18

申请号：US10121176

申请日：2002-04-11

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

IPC分类号： H05K330

CPC分类号： H01R13/2421 ,  G01R1/0466 ,  G01R1/0483 ,  H01L2924/0002 ,  H01R12/714 ,  H01R2201/20 ,  H05K7/1061 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  Y10T29/49224 ,  Y10T29/53174 ,  H01L2924/00

摘要： In a socket to test semiconductor die, a recessed socket contact that avoids pinching the die contacts is diclosed. The socket contacts allow for smaller socket holes and, allow denser contact spacing. A variety of embodiments are presented that are suitable for use depending on the spacing between the conducters. For more closely spaced conductors, the body of the socket contact comprises a head, a spring coupled to the head, and a shaft coupled to the spring. No outer shell is needed for the spring, as the nonconductive sides of the socket hole serve that function. For conductors spaced further apart, the body of the socket contact comprises a metal shaft having an aperture. Compression causes the shaft to close around the slit, thereby decreasing the amount of lateral buckling. For even more densly spaced contacts, semiconductor fabrication techniques are used to construct a dense array of contacts.

摘要翻译： 在用于测试半导体管芯的插座中，隐藏了避免挤压模具触头的凹入插座触点。 插座触点允许更小的插座孔，并允许更密集的接触间距。 呈现出根据导体之间的间距适合使用的各种实施例。 对于更紧密间隔的导体，插座触头的主体包括头部，联接到头部的弹簧和联接到弹簧的轴。 弹簧不需要外壳，因为插座孔的不导电侧面具有这种功能。 对于间隔更远的导体，插座触头的主体包括具有孔的金属轴。 压缩使轴在缝隙周围闭合，从而减少侧向屈曲的量。 对于更密集间隔的触点，使用半导体制造技术来构造密集的触点阵列。

公开(公告)号：US06407451B2

公开(公告)日：2002-06-18

申请号：US09769983

申请日：2001-01-25

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

IPC分类号： H01L2304

CPC分类号： H01L23/13 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13339 ,  H01L2224/16237 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/013

摘要： A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface is disclosed. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array, or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

摘要翻译： 公开了一种芯片级封装，其由具有层压到其有源表面上的硅片的半导体管芯组成。 模具的接合焊盘通过微机械加工通过坯件的孔进入。 该封装可以与引线接合使用，或者可以将焊料或其它导电凸块放置在用于倒装芯片应用的空白孔中。 此外，封装可以用于将管芯的外部连接重新路由到其他位置，例如集中式球栅阵列，或用于直接或离散管芯连接（DDC）到载体的边缘连接装置。 优选的是，芯片级封装形成在晶片级，作为如此形成的多个封装之一，其形成有晶片级坯料，并且整个晶片被烧入并测试以识别已知的良好裸片（KGD ），然后将晶片层压板分离成单个包装。

公开(公告)号：US06400174B2

公开(公告)日：2002-06-04

申请号：US09749173

申请日：2000-12-27

申请人： Salman Akram ,  Warren M. Farnworth ,  Michael E. Hess ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  Michael E. Hess ,  David R. Hembree

IPC分类号： G01R3126

CPC分类号： G01R1/0483 ,  G01R31/2886 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/8592 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

摘要： A test system for testing semiconductor components includes an interconnect having contacts for making temporary electrical connections with terminal contacts on the components. The interconnect contacts can be configured to electrically engage planar terminal contacts (e.g., bond pads, test pads) or bumped terminal contacts (e.g., solder bumps, solder balls) on the components. The test system also includes an alignment member for aligning the components to the interconnect. Different embodiments of the alignment member include: a curable polymer material molded in place on the interconnect; an alignment opening formed as an etched pocket in a substrate of the interconnect; and a separate fence attached to the interconnect using an alignment fixture.

公开(公告)号：US06356098B1

公开(公告)日：2002-03-12

申请号：US09394960

申请日：1999-09-10

申请人： Salman Akram ,  C. Patrick Doherty ,  Warren M. Farnworth ,  David R. Hembree

发明人： Salman Akram ,  C. Patrick Doherty ,  Warren M. Farnworth ,  David R. Hembree

IPC分类号： G01R3126

CPC分类号： G01R31/2886 ,  G01R1/07378

摘要： A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. In an illustrative embodiment the force applying member includes spring loaded electrical connectors in physical and electrical contact with the pin contacts. Alternately, the force applying member includes a compressible pad for multiple pin contacts, or separate compressible pads for each pin contact. A penetration depth of the pin contacts into the die contacts is controlled by selecting a spring force of the force applying member, and an amount of Z-direction overdrive of the pin contacts into the die contacts.

摘要翻译： 提供了用于测试半导体晶片的探针卡，测试方法和采用探针卡的测试系统。 探针卡包括：基底; 引脚触点的图案可滑动地安装到基板上; 以及用于使所述销触点偏压以与所述晶片上的芯片触点电接触的施力部件。 在示例性实施例中，施力构件包括与销触点物理和电接触的弹簧加载的电连接器。 或者，施力构件包括用于多个针接触的可压缩垫，或者每个销接触的单独的可压缩垫。 通过选择力施加部件的弹簧力来控制销接触到模具接触部中的穿透深度，并且销的Z方向过驱动量接触到模具接触件中。

公开(公告)号：US06353328B2

公开(公告)日：2002-03-05

申请号：US09745093

申请日：2000-12-20

申请人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

IPC分类号： G01R3102

CPC分类号： G01R1/04 ,  H01L2924/15311

摘要： A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.

摘要翻译： 提供了一种用于测试半导体部件的测试系统，例如凸起的芯片和芯片级封装。 测试系统包括用于保持一个或多个部件的基座和用于与部件进行临时电连接的互连。 测试系统还包括具有用于将部件对准互连的对准表面的对准夹具。 另外，组件可以包括对准构件，诸如斜面边缘，凸块或构造成与对准表面相互作用的柱。 对准夹具可以形成为聚合物层，例如抗蚀剂层，其使用晶片级制造工艺沉积，显影，然后固化。 对准表面可以是构造成接合部件边缘的聚合物层中的开口，或者交替地接合对准部件。

公开(公告)号：US06255840B1

公开(公告)日：2001-07-03

申请号：US09304941

申请日：1999-05-04

申请人： David R. Hembree ,  Salman Akram ,  Derek Gochnour ,  Warren M. Farnworth

发明人： David R. Hembree ,  Salman Akram ,  Derek Gochnour ,  Warren M. Farnworth

IPC分类号： G01R3126

CPC分类号： G01R1/0483 ,  H01L2224/48091 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

摘要： A package, system and method for testing semiconductor dice are provided. The package include a base for retaining the die, and an interconnect having contact members for establishing temporary electrical connections with the die. Electrical paths are formed between terminal contacts on the base, and the contact members on the interconnect, by wires that are wire bonded to conductors on the base and interconnect. The package includes a protective member for protecting the wires and associated wire bonds during assembly, disassembly and handling of the package. The protective member can be formed as a plate mounted to the base and configured to cover the wires and wire bonds. Alternately the protective member can comprise an encapsulating material such as an epoxy resin or silicone elastomer deposited on the wires and wire bonds and then cured.

摘要翻译： 提供了一种用于测试半导体晶片的封装，系统和方法。 该封装包括用于保持裸片的基座和具有与模具建立临时电连接的接触构件的互连。 通过引线接合到基座上的导体和互连件上的导线，在基座上的端子触头与互连件上的接触部件之间形成电气路径。 该包装包括用于在组装，拆卸和处理包装过程中保护电线和相关联的线接合的保护构件。 保护构件可以形成为安装到基座并被构造成覆盖电线和引线接合的板。 替代地，保护构件可以包括诸如环氧树脂或硅氧烷弹性体的封装材料，其沉积在电线和引线键上，然后固化。

公开(公告)号：US06229324B1

公开(公告)日：2001-05-08

申请号：US09365461

申请日：1999-08-02

申请人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

IPC分类号： G01R3102

CPC分类号： G01R1/04 ,  H01L2924/15311

摘要： A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.

公开(公告)号：US06222379B1

公开(公告)日：2001-04-24

申请号：US09093357

申请日：1998-06-08

申请人： Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram

发明人： Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram

IPC分类号： G01R3102

CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.

摘要翻译： 提供了一种用于封装和测试半导体管芯的方法。 该方法包括形成具有与常规塑料或陶瓷半导体封装相同的尺寸，形状和引线配置的裸片的临时封装。 临时包装可用于使用标准设备对模具进行老化测试。 然后可以将模具从包装中取出并被认证为已知的好的模具。 在说明性实施例中，封装形成为SOJ构造。 该包装包括底座，互连和力施加机构。 封装基底可以使用陶瓷层压工艺或Cerdip形成工艺由陶瓷或塑料制成。

公开(公告)号：US06215322B1

公开(公告)日：2001-04-10

申请号：US08888471

申请日：1997-07-07

申请人： Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram

发明人： Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram

IPC分类号： G01R3102

CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.