公开(公告)号：US20080305576A1

公开(公告)日：2008-12-11

申请号：US11759475

申请日：2007-06-07

申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC分类号： H01L21/02

CPC分类号： H05K1/0271 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H05K3/0052 ,  H05K3/28 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/09136 ,  H01L2924/00 ,  H01L2924/00012

摘要： A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process.

摘要翻译： 公开了一种可在多个处理工具内制造多个集成电路封装轮廓的面板。 面板包括模制化合物和/或基底的暴露表面中的凹陷部分。 该凹槽减轻了由衬底和施加到集成电路周围的衬底的模塑料之间的不同膨胀系数引起的应力。 在实施例中，凹口可以形成为刻痕到模制化合物或基底的表面中的线。 或者，在施加焊接掩模的工艺期间，可以在衬底上的焊料掩模中形成凹部，或者在封装工艺期间可以在模制化合物中形成凹部。

公开(公告)号：US20080131999A1

公开(公告)日：2008-06-05

申请号：US11694705

申请日：2007-03-30

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/85186 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer. After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. The first semiconductor layer may be wire-bonded to the substrate using bond wires sheathed within an electrical insulator. As the bond wires are surrounded by an electrical insulator, the intermediate layer need not space the wire bond loops from the second semiconductor die as in the prior art, and the apex of bond wires may come into contact with the dielectric layer. The intermediate layer may thus be made thinner in comparison to conventional stacked semiconductor die configurations.

摘要翻译： 公开了一种低剖面半导体封装，其包括至少安装到衬底的第一和第二层叠半导体管芯。 第一半导体管芯和第二半导体管芯由薄型中间粘合剂层隔开。 在施加中间层之后，第二半导体管芯可以堆叠在中间层的顶部上。 第一半导体层可以使用在电绝缘体中包覆的接合线引线键合到基板上。 由于接合线被电绝缘体包围，如现有技术那样，中间层不需要将第二半导体管芯的引线接合环空间，并且接合线的顶点可能与介电层接触。 因此，与传统的堆叠半导体管芯配置相比，中间层可以被制成更薄。

公开(公告)号：US20080128880A1

公开(公告)日：2008-06-05

申请号：US11694713

申请日：2007-03-30

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/85186 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer. After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. The first semiconductor layer may be wire-bonded to the substrate using bond wires sheathed within an electrical insulator. As the bond wires are surrounded by an electrical insulator, the intermediate layer need not space the wire bond loops from the second semiconductor die as in the prior art, and the apex of bond wires may come into contact with the dielectric layer. The intermediate layer may thus be made thinner in comparison to conventional stacked semiconductor die configurations.

摘要翻译： 公开了一种低剖面半导体封装，其包括至少安装到衬底的第一和第二层叠半导体管芯。 第一半导体管芯和第二半导体管芯由薄型中间粘合剂层隔开。 在施加中间层之后，第二半导体管芯可以堆叠在中间层的顶部上。 第一半导体层可以使用在电绝缘体中包覆的接合线引线键合到基板上。 由于接合线被电绝缘体包围，所以如现有技术那样，中间层不需要将第二半导体管芯的引线接合环空间，并且接合线的顶点可能与介电层接触。 因此，与传统的堆叠半导体管芯配置相比，中间层可以被制成更薄。

公开(公告)号：US07375415B2

公开(公告)日：2008-05-20

申请号：US11170897

申请日：2005-06-30

申请人： Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

发明人： Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49551 ,  H01L23/49558 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.

摘要翻译： 公开了一种用于半导体封装的引线框架，其包括从引线框架的一侧延伸到引线框架的相反侧的电引线，其中可以在引线框架的第二侧与半导体管芯进行电连接。 半导体管芯可以被支撑在引导框架上延伸的引线上。 封装还可以包括固定到电引线上的间隔层，以强化半导体封装并防止在封装成型期间电引线的暴露。

公开(公告)号：US20080081455A1

公开(公告)日：2008-04-03

申请号：US11538220

申请日：2006-10-03

申请人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

发明人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

IPC分类号： H01L21/44

CPC分类号： H01L21/4846 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00014

摘要： Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.

摘要翻译： 公开了形成包括单面基板的半导体封装的方法。 在本发明的第一实施例中，衬底可以在衬底的顶表面上，即在衬底的与安装裸片相同的一侧上包括导电层。 在本发明的第二实施例中，衬底可以包括在衬底的底部上的导电层，即衬底的安装模具的相反侧。

公开(公告)号：US20080064272A1

公开(公告)日：2008-03-13

申请号：US11938950

申请日：2007-11-13

申请人： Robert Miller ,  Hem Takiar ,  Joel Jacobs ,  Robert Howard ,  Motohide Hatanaka ,  Robert Wallace ,  Edwin Cuellar ,  Eliyahou Harari ,  Matt Peterson

发明人： Robert Miller ,  Hem Takiar ,  Joel Jacobs ,  Robert Howard ,  Motohide Hatanaka ,  Robert Wallace ,  Edwin Cuellar ,  Eliyahou Harari ,  Matt Peterson

IPC分类号： H01R13/46

CPC分类号： G06K19/077 ,  G06K19/07732 ,  G06K19/07733 ,  G06K19/07741 ,  G06K19/07743 ,  H01R13/447 ,  H01R27/00

摘要： Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB). One memory card standard that can be followed is that of the Secure Digital (SD) card. The cards can thus be used with different hosts that are compatible with one set of contacts but not the other. A cover that is hinged to the card to normally cover one set of contacts can be rotated out of the way by hand when that set of contacts is being used.

摘要翻译： 封闭的可重新编程的非易失性存储卡包括至少两组电触点，内部存储器与之连接。 两组触点具有不同的图案，优选地根据两种不同的接触标准，例如存储卡标准和通用串行总线（USB）的标准。 可以遵循的一种存储卡标准是安全数字（SD）卡的标准。 因此，这些卡可以与与一组联系而不是另一组相容的不同主机使用。 当使用该组触点时，铰接到卡上的盖通常覆盖一组触点可以手动旋转。

公开(公告)号：US20080054445A1

公开(公告)日：2008-03-06

申请号：US11930816

申请日：2007-10-31

申请人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

发明人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L23/562 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05015 ,  H01L2224/05023 ,  H01L2224/0605 ,  H01L2224/06151 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/15333 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

摘要翻译： 形成在半导体管芯封装中的衬底的第一侧上的刚性波形图案。 刚性波形图案与形成在基板的第二侧上的接触指状物对准并覆盖在其上。 当模制过程中衬底和裸片被封装时，刚性波形有效地减少了模具的变形和应力，从而大大减轻了模具开裂。

公开(公告)号：US20080001266A1

公开(公告)日：2008-01-03

申请号：US11427695

申请日：2006-06-29

申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC分类号： H01L21/00

CPC分类号： H01L24/49 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

摘要翻译： 公开了一种包括多个堆叠的半导体封装的电子部件。 第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。 第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

公开(公告)号：US20070262434A1

公开(公告)日：2007-11-15

申请号：US11782102

申请日：2007-07-24

申请人： Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar ,  Jack Chien ,  Meng-Ju Tsai

发明人： Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar ,  Jack Chien ,  Meng-Ju Tsai

IPC分类号： H01L23/02

CPC分类号： H01L23/49805 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/142 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09963 ,  H05K2201/1053 ,  H05K2201/10727 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes lie along the cut line between adjacent packages so that, upon singulation, the filled through holes are cut and a portion of the filled through-holes are exposed at the side edges of the singulated packages. These exposed portions of the filled through-holes form vertical surface mount technology (SMT) pads. After the semiconductor packages are singulated and the SMT pads are defined in the side edges, SMT is used to solder the SMT pads of a first semiconductor package to the respective SMT pads of a second semiconductor package to structurally and electrically couple the two packages together side-by-side.

摘要翻译： 公开了一种电子部件，其包括以并排配置焊接在一起的多个半导体封装。 包装在基板上进行批量处理。 面板包括穿过面板钻出的多个通孔，随后填充有诸如铜或金的金属。 这些填充的通孔沿着相邻封装之间的切割线位于相邻封装之间的切割线处，使得在分离时，填充的通孔被切割并且一部分填充的通孔在单个封装的侧边缘处露出。 填充的通孔的这些暴露部分形成垂直表面贴装技术（SMT）焊盘。 在半导体封装被单个化并且SMT焊盘限定在侧边缘中之后，使用SMT来将第一半导体封装的SMT焊盘焊接到第二半导体封装的相应SMT焊盘，以将两个封装结合和电耦合在一起 旁边。

公开(公告)号：US20070218588A1

公开(公告)日：2007-09-20

申请号：US11750768

申请日：2007-05-18

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each other or to a substrate. These improved approaches are particularly useful for stacking same size (and often same function) integrated circuit dies within integrated circuit packages. One example of such an integrated circuit package is a non-volatile memory integrated circuit package that contains multiple, like-sized memory storage integrated circuit dies arranged in a stack.

摘要翻译： 公开了用于在集成电路封装内堆叠集成电路管芯的改进的技术。 这些改进的技术允许集成电路封装内的集成电路管芯的堆叠密度更高。 此外，改进的堆叠技术允许用于将各种集成电路管芯彼此或与衬底电连接的常规焊接技术。 这些改进的方法对于在集成电路封装内堆叠相同尺寸（并且通常是相同功能的）集成电路管芯特别有用。 这种集成电路封装的一个例子是非易失性存储器集成电路封装，其包含堆叠地布置的多个相同大小的存储器集成电路管芯。