公开(公告)号：US06343001B1

公开(公告)日：2002-01-29

申请号：US09655381

申请日：2000-09-05

申请人： Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

发明人： Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

IPC分类号： H01G4228

CPC分类号： H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0759

摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.

摘要翻译： 提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。 通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。 第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。 在第一和第二外部平面的每一个中形成至少一个间隙孔。 可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。 本发明还涉及通过这些方法形成的结构。

公开(公告)号：US5796587A

公开(公告)日：1998-08-18

申请号：US662164

申请日：1996-06-12

申请人： John M. Lauffer ,  Konstantinos Papathomas

发明人： John M. Lauffer ,  Konstantinos Papathomas

IPC分类号： H05K1/16 ,  H05K3/42 ,  H05K3/46

CPC分类号： H05K1/162 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0759 ,  H05K3/429 ,  H05K3/4611 ,  Y10T29/43 ,  Y10T29/435

摘要： A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

摘要翻译： 提供了一种用于制造要嵌入电子电路封装的电容器的方法，包括以下步骤：选择第一导体箔，选择电介质材料，在第一导体箔的至少一侧上涂覆电介质材料， 在介质材料涂层的顶部具有第二导体箔的箔。 还要求保护的是包含至少一个根据本发明制造的嵌入式电容器的电子电路封装。

公开(公告)号：US5027253A

公开(公告)日：1991-06-25

申请号：US506640

申请日：1990-04-09

申请人： John M. Lauffer ,  Richard A. Schumacher

发明人： John M. Lauffer ,  Richard A. Schumacher

IPC分类号： H01G4/33 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46

CPC分类号： H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K3/429 ,  H05K3/4611 ,  Y10S257/916 ,  Y10T29/435

摘要： Disclosed is a multilayer circuit package having a buried thin film capacitor. The circuit package includes at least a power core, a ground core, a first signal core, a second signal core, and the integral, buried, thin film capacitor. The integral, buried, thin film capacitor serves to capacitively couple the first and second signal cores. Structurally, the first signal core includes at least one first wire that terminates in at least one first electrode, while the second signal core includes at least one second wire that terminates in at least one second electrode. At least a portion of the first electrode overlays at least a portion of the first electrode overlays at least a portion of the second electrode and is separated therefrom by a thin film of a dielectric material. The first electrode, the second electrode, and the thin film of dielectric material define the integral buried capacitor. The thin film capacitor is prepared by thin film methodology, with epitaxial deposition of the dielectric.

公开(公告)号：US07870664B2

公开(公告)日：2011-01-18

申请号：US11797236

申请日：2007-05-02

申请人： Rabindra N. Das ,  John M. Lauffer ,  Vova R. Markovich

发明人： Rabindra N. Das ,  John M. Lauffer ,  Vova R. Markovich

IPC分类号： H05K3/30

CPC分类号： H05K1/167 ,  H01G4/206 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/095 ,  H05K1/162 ,  H05K3/0023 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49089 ,  Y10T29/49091 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.

摘要翻译： 一种制造电路化基板的方法，包括由包括聚合物树脂的材料和包括至少一种金属组分和至少一种陶瓷组分的混合物的纳米粉末的量组成的电阻器。 陶瓷部件可以是铁电陶瓷和/或高表面积陶瓷和/或透明氧化物和/或掺杂亚锰酸盐。 或者，材料将包括聚合物树脂和纳米粉末，其中纳米粉末包含至少一种金属涂覆的陶瓷和/或至少一种氧化物涂覆的金属组分。 还提供了使用这种电路化基板的电气组件（基板和至少一个电气部件）以及信息处理系统（例如，个人计算机）。

公开(公告)号：US20100060381A1

公开(公告)日：2010-03-11

申请号：US12283146

申请日：2008-09-09

申请人： Rabindra N. Das ,  John M. Lauffer ,  Irving Memis ,  Steven G. Rosser

发明人： Rabindra N. Das ,  John M. Lauffer ,  Irving Memis ,  Steven G. Rosser

IPC分类号： H03H7/00 ,  H05K3/30

CPC分类号： H05K1/162 ,  H05K1/023 ,  H05K1/0234 ,  H05K1/167 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/0361 ,  Y10T29/4913 ,  Y10T428/12493 ,  Y10T428/24917 ,  Y10T428/31511

摘要： A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

摘要翻译： 多层嵌入式电容和电阻基板芯。 提供至少一层电阻材料。 电阻材料层具有嵌入其中的导电材料层。 在电阻材料层上设置至少一层高介电常数的电容材料层。 通孔由激光形成。

公开(公告)号：US20090178271A1

公开(公告)日：2009-07-16

申请号：US12007820

申请日：2008-01-16

申请人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

发明人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

IPC分类号： H01C17/06

CPC分类号： H01C17/06 ,  H01C17/24 ,  H05K1/0268 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/0361 ,  H05K2203/171 ,  Y10T29/49099 ,  Y10T29/49101

摘要： A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.

摘要翻译： 一种制造电路化衬底的方法，其包括形成具有近似电阻值的多个单独的膜电阻器作为衬底的至少一个电路的一部分，测量代表性（样品）电阻器的电阻以限定其电阻，利用这些测量 确定位于相对于代表性电阻器确定的接近度的其它剩余膜电阻器的对应精确宽度，使得这些剩余的膜电阻器将包括限定的电阻值，然后选择性地隔离这些剩余膜电阻器的电阻材料的限定部分，同时 同时限定电阻材料的精确宽度，以使这些薄膜电阻器具有限定的电阻。

公开(公告)号：US20080151515A1

公开(公告)日：2008-06-26

申请号：US11797236

申请日：2007-05-02

申请人： Rabindra N. Das ,  John M. Lauffer ,  Vova R. Markovich

发明人： Rabindra N. Das ,  John M. Lauffer ,  Vova R. Markovich

IPC分类号： H05K1/16 ,  H05K1/18 ,  H05K3/10

CPC分类号： H05K1/167 ,  H01G4/206 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/095 ,  H05K1/162 ,  H05K3/0023 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49089 ,  Y10T29/49091 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.

摘要翻译： 一种制造电路化基板的方法，包括由包括聚合物树脂的材料和包括至少一种金属组分和至少一种陶瓷组分的混合物的纳米粉末的量组成的电阻器。 陶瓷部件可以是铁电陶瓷和/或高表面积陶瓷和/或透明氧化物和/或掺杂亚锰酸盐。 或者，材料将包括聚合物树脂和纳米粉末，其中纳米粉末包含至少一种金属涂覆的陶瓷和/或至少一种氧化物涂覆的金属组分。 还提供了使用这种电路化基板的电气组件（基板和至少一个电气部件）以及信息处理系统（例如，个人计算机）。

公开(公告)号：US06996903B2

公开(公告)日：2006-02-14

申请号：US10641182

申请日：2003-08-14

申请人： Donald S. Farquhar ,  Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

发明人： Donald S. Farquhar ,  Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

IPC分类号： H01K3/10

CPC分类号： H05K3/429 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09645 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

公开(公告)号：US06830627B1

公开(公告)日：2004-12-14

申请号：US09274935

申请日：1999-03-23

申请人： Kathleen L. Covert ,  John M. Lauffer ,  Peter A. Moschak

发明人： Kathleen L. Covert ,  John M. Lauffer ,  Peter A. Moschak

IPC分类号： B08B700

CPC分类号： C11D7/10 ,  C11D7/08 ,  C11D7/16 ,  C11D11/0047 ,  C23F1/18 ,  C23G1/103 ,  H05K1/167 ,  H05K3/383 ,  H05K2203/0796

摘要： The present invention is a persulfate microetchant composition especially useful for removing impurities from copper surfaces during fabrication of microelectronic packages. The microetchant formulation is characterized by its ability to selectively clean copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this microetchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate microetchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature. A preferred etchant composition is 100 gm/liter sodium persulfate, 3 volume % phosphoric acid and 0.058 molar sodium phosphate dibasic.

摘要翻译： 本发明是一种特别适用于在制造微电子封装期间从铜表面去除杂质的过硫酸盐微蚀剂组合物。 微蚀剂制剂的特征在于其在镍，镍 - 磷和贵金属合金存在下选择性地清洗铜的能力。 此外，在该微蚀刻 - 衬底系统中不会发生有害的电偶蚀刻，因此基本上不会发生铜的底切。 高选择性和无底切的组合允许微电子制造工艺的简化和微电子封装，特别是较高密度电路的设计特征的显着改进。 过硫酸盐微提取剂组合物用酸和磷酸盐稳定，以提供稳定，快速作用，环境可接受，具有高容量的方法，并且可以在室温下进行。 优选的蚀刻剂组合物为100g /升过硫酸钠，3体积％磷酸和0.058摩尔磷酸氢二钠。

公开(公告)号：US06689543B2

公开(公告)日：2004-02-10

申请号：US10073558

申请日：2002-02-11

申请人： John S. Kresge ,  John M. Lauffer ,  David J. Russell

发明人： John S. Kresge ,  John M. Lauffer ,  David J. Russell

IPC分类号： G03C556

CPC分类号： H05K3/0032 ,  B23K2103/42 ,  B23K2103/50 ,  B41M5/24 ,  H05K1/0326 ,  H05K1/0373 ,  H05K2201/0112 ,  Y10S430/146

摘要： An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.

摘要翻译： 通过向树脂中添加染料或染料，在用于激光烧蚀树脂的激光器的发射波长处具有显着的能量吸收，提供了表现出良好的激光烧蚀和对衬底的良好粘合性的环氧树脂。 将含有染料或染料的树脂涂覆在基材上并固化，或在固化条件下层压到基材上。 通过激光烧蚀在所述固化膜中形成所需的开口。 这允许使用最佳技术来形成微通孔。