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    FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS
    92.
    发明申请
    FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS 有权
    固定曲面力加载机械薄膜

    公开(公告)号：US20130052798A1

    公开(公告)日：2013-02-28

    申请号：US13215738

    申请日：2011-08-23

    申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

    IPC分类号： H01L21/30

    CPC分类号： H01L21/30 ,  H01L31/1892 ,  Y02E10/50

    摘要： A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

    摘要翻译： 提供了一种剥落方法，其包括在基底表面上沉积应力层，并使应力层与平面转移接触。 然后，平面转移表面沿着平行于并且具有从基底基板的上表面垂直偏移的平面穿过。 平面转移表面在从基底基板的第一边缘到基底基板的相对的第二边缘的方向上穿过，以将基底基板切割并将基底基板的剥离部分转印到平面转印表面。 平面转移面沿着平面移动的平面与基底基板的上表面之间的垂直偏移是固定的距离。 垂直偏移的固定距离提供均匀的剥落力。 还提供了包括转印辊的剥落方法。

    SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT
    95.
    发明申请
    SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT 有权
    自对准III-V MOSFET扩散区和类硅合金接触

    公开(公告)号：US20130001659A1

    公开(公告)日：2013-01-03

    申请号：US13603739

    申请日：2012-09-05

    申请人： Cheng-Wei Cheng ,  Augustin J. Hong ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu

    发明人： Cheng-Wei Cheng ,  Augustin J. Hong ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu

    IPC分类号： H01L29/78

    CPC分类号： H01L21/2258 ,  H01L21/246 ,  H01L21/28575 ,  H01L29/41775 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522

    摘要： A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.

    摘要翻译： 金属氧化物半导体场效应晶体管及其形成方法包括在与栅极叠层相邻的衬底上的曝光部分，在栅极叠层上形成掺杂剂层，并在暴露并退火掺杂剂层驱动的部分中与衬底接触 掺杂到衬底中以在衬底中形成自对准掺杂剂区域。 去除掺杂剂层。 在栅极叠层上沉积含金属层，并在暴露部分与衬底接触。 对含金属层进行退火以将金属驱动到衬底中，以在掺杂区域内的衬底中形成的金属合金中形成自对准接触区域。 然后去除金属层。

    SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING
    97.
    发明申请
    SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING 审中-公开
    选择性外来成长通过孵化时间工程

    公开(公告)号：US20120295417A1

    公开(公告)日：2012-11-22

    申请号：US13109567

    申请日：2011-05-17

    申请人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

    发明人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66628 ,  H01L21/0237 ,  H01L21/02524 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/78

    摘要： A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.

    摘要翻译： 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

    NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS
    98.
    发明申请
    NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS 有权

    公开(公告)号：US20120289035A1

    公开(公告)日：2012-11-15

    申请号：US13555252

    申请日：2012-07-23

    申请人： Maha M. Khayyat ,  Devendra K. Sadana ,  Brent A. Wacaser

    发明人： Maha M. Khayyat ,  Devendra K. Sadana ,  Brent A. Wacaser

    IPC分类号： H01L21/20

    CPC分类号： H01L29/0676 ,  H01L21/20 ,  H01L21/30 ,  H01L29/02 ,  H01L29/20 ,  H01L29/66

    摘要： A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.