公开(公告)号：US08841167B1

公开(公告)日：2014-09-23

申请号：US13951772

申请日：2013-07-26

Applicant: Yuping Gong ,  Yan Xun Xue ,  Liang Zhao

Inventor： Yuping Gong ,  Yan Xun Xue ,  Liang Zhao

IPC: H01L21/50 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L24/34 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40475 ,  H01L2224/4103 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Abstract translation: 公开了一种用于共包装高侧（HS）和低侧（LS）半导体芯片）的半导体封装方法。 HS和LS半导体芯片附接到引线框架的两个相对侧，LS芯片的底部漏电极连接到引线框架的顶侧，HS芯片的顶部源极连接到 引线框架通过焊球。 HS芯片，引线框架和LS芯片的堆叠配置减少了封装尺寸。 覆盖暴露在封装主体外部的HS芯片的底部的底部金属层提供电连接和热传导。

公开(公告)号：US20140264805A1

公开(公告)日：2014-09-18

申请号：US13833341

申请日：2013-03-15

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495 ,  H01L21/78

CPC classification number: H01L23/49562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Abstract translation: 一种制造半导体封装器件的方法包括将引线框架安装在模制半导体芯片的底部，该底部具有覆盖半导体芯片的顶面的第一塑料封装体，用第二塑料封装体封装引线框和半导体芯片 导电接触体的顶表面电连接到半导体芯片的顶表面上的电极，并暴露在组件结构的顶表面上的导电焊盘，以通过导电接触体提供与电极的外部电连接。

公开(公告)号：US08778735B1

公开(公告)日：2014-07-15

申请号：US13931854

申请日：2013-06-29

Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC: H01L21/00 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L21/304 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/27 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

Abstract translation: WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

公开(公告)号：US20140117523A1

公开(公告)日：2014-05-01

申请号：US13663694

申请日：2012-10-30

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/4952 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2221/68327 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13794 ,  H01L2224/13839 ,  H01L2224/1403 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40248 ,  H01L2224/40499 ,  H01L2224/405 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/00012

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract translation: 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。

公开(公告)号：US08710648B2

公开(公告)日：2014-04-29

申请号：US13429263

申请日：2012-03-23

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L23/04

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/03

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract translation: 一种用于提供具有增加的接触焊盘区域的晶片级封装的方法，包括以下步骤：在晶片顶表面上形成第一封装层，研磨晶片背面并蚀刻通孔，沉积金属以填充通孔并覆盖晶片背面， 从晶片背面切割晶片，形成分开每个芯片的多个沟槽，然后沉积填充沟槽并覆盖晶片背面金属的第二封装层，减小第一封装层厚度以露出填充凹槽的第二封装层并形成多个 接触垫重叠在第一包装层上，然后切割槽中的第二包装层以形成单个包装。

公开(公告)号：US08563361B2

公开(公告)日：2013-10-22

申请号：US13547358

申请日：2012-07-12

Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

Abstract translation: WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

公开(公告)号：US08519525B2

公开(公告)日：2013-08-27

申请号：US12846034

申请日：2010-07-29

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC: H01L23/495

CPC classification number: H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40248 ,  H01L2224/40249 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

Abstract translation: 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。

公开(公告)号：US08519520B2

公开(公告)日：2013-08-27

申请号：US13302077

申请日：2011-11-22

Applicant: YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

Inventor： YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

IPC: H01L23/495 ,  H01L23/34

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Abstract translation: 公开了一种用于共包装高侧（HS）和低侧（LS）半导体芯片）的半导体封装方法。 HS和LS半导体芯片附接到引线框架的两个相对侧，LS芯片的底部漏电极连接到引线框架的顶侧，HS芯片的顶部源极连接到 引线框架通过焊球。 HS芯片，引线框架和LS芯片的堆叠配置减少了封装尺寸。 覆盖暴露在封装主体外部的HS芯片的底部的底部金属层提供电连接和热传导。

公开(公告)号：US08482048B2

公开(公告)日：2013-07-09

申请号：US12947107

申请日：2010-11-16

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L23/5223 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.

Abstract translation: 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。

公开(公告)号：US20130075884A1

公开(公告)日：2013-03-28

申请号：US13302077

申请日：2011-11-22

Applicant: YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

Inventor： YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Abstract translation: 公开了一种用于共包装高侧（HS）和低侧（LS）半导体芯片）的半导体封装方法。 HS和LS半导体芯片附接到引线框架的两个相对侧，LS芯片的底部漏电极连接到引线框架的顶侧，HS芯片的顶部源极连接到 引线框架通过焊球。 HS芯片，引线框架和LS芯片的堆叠配置减少了封装尺寸。 覆盖暴露在封装主体外部的HS芯片的底部的底部金属层提供电连接和热传导。