公开(公告)号：US07204008B2

公开(公告)日：2007-04-17

申请号：US10609263

申请日：2003-06-26

申请人： Benjamin N. Eldridge

发明人： Benjamin N. Eldridge

IPC分类号： G01R31/28

CPC分类号： G01R31/31926 ,  G01R1/07314 ,  G01R31/318505 ,  G01R31/31905 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  Y10T29/49002 ,  Y10T29/49004 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00014

摘要： An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.

摘要翻译： 通过可拆卸地将集成电路连接到模块基板来组装电子模块。 然后以特定的操作速度测试模块。 如果模块在测试速度下无法正常工作，则会导致故障的集成电路或电路被更换为新的集成电路，并重新测试模块。 一旦确定模块以测试速度正确运行，模块可能被评定为以测试速度运行并出售，或者模块可以以更高的速度进行测试。

公开(公告)号：US20070013401A1

公开(公告)日：2007-01-18

申请号：US11458375

申请日：2006-07-18

申请人： Igor Khandros ,  David Pedersen

发明人： Igor Khandros ,  David Pedersen

IPC分类号： G01R31/26

CPC分类号： G01R31/2886 ,  G01R31/287 ,  G01R31/2874 ,  G01R31/318511 ,  H01L2924/01078 ,  H01L2924/01079

摘要： Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

摘要翻译： 用于执行半导体器件的晶片级老化和测试的技术包括具有有源电子部件的测试基板，例如安装到互连基板或并入其中的ASIC，实现ASIC和多个器件之间的互连的金属弹簧接触元件 在测试晶片（WUT）上的测试（DUT）都被置于真空容器中，使得ASIC可以在与DUT的老化温度无关并且显着低于DUT的老化温度的温度下工作。 弹簧接触元件可以被安装到DUT或ASIC上，并且可以扇出来放松对ASIC和DUT的对准和互连的容限约束。 还描述了物理对准技术。

公开(公告)号：US20060290367A1

公开(公告)日：2006-12-28

申请号：US11165833

申请日：2005-06-24

申请人： Eric Hobbs ,  Benjamin Eldridge ,  Lunyu Ma ,  Gaetan Mathieu ,  Steven Murphy ,  Makarand Shinde ,  Alexander Slocum

发明人： Eric Hobbs ,  Benjamin Eldridge ,  Lunyu Ma ,  Gaetan Mathieu ,  Steven Murphy ,  Makarand Shinde ,  Alexander Slocum

IPC分类号： G01R31/02

CPC分类号： G01R31/2886 ,  G01R1/073 ,  G01R31/31905 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49208 ,  Y10T29/49222

摘要： A probe card assembly comprises multiple probe substrates attached to a mounting assembly. Each probe substrate includes a set of probes, and together, the sets of probes on each probe substrate compose an array of probes for contacting a device to be tested. Adjustment mechanisms are configured to impart forces to each probe substrate to move individually each substrate with respect to the mounting assembly. The adjustment mechanisms may translate each probe substrate in an “x,” “y,” and/or “z” direction and may further rotate each probe substrate about any one or more of the forgoing directions. The adjustment mechanisms may further change a shape of one or more of the probe substrates. The probes can thus be aligned and/or planarized with respect to contacts on the device to be tested.

摘要翻译： 探针卡组件包括附接到安装组件的多个探针基板。 每个探针衬底包括一组探针，并且每个探针衬底上的探针组合在一起组成一组探针，用于接触待测试的器件。 调整机构构造成赋予每个探针基板以相对于安装组件分别移动每个基板的力。 调节机构可以将每个探针基板转换成“x”，“y”和/或“z”方向，并且可以进一步围绕前述方向上的任何一个或多个旋转每个探针基板。 调节机构可以进一步改变一个或多个探针基板的形状。 因此，探针可以相对于要测试的装置上的触点对准和/或平坦化。

公开(公告)号：US20060279300A1

公开(公告)日：2006-12-14

申请号：US11423808

申请日：2006-06-13

申请人： Igor Khandros ,  A. Sporck ,  Benjamin Eldridge

发明人： Igor Khandros ,  A. Sporck ,  Benjamin Eldridge

IPC分类号： G01R31/02

CPC分类号： H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07364 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05599

摘要： In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

摘要翻译： 在探针卡组件中，可以将一系列探针元件排列在硅空间变压器上。 硅空间变压器可以以与半导体器件的间距相当的非常紧密的间距的主要触点阵列制造。 一个优选的主要接触是弹性弹簧接触。 空间变压器中的导电元件以更放松的间距被路由到第二触点。 在一个优选实施例中，第二触点适于直接连接带状电缆，带状电缆又可连接以提供对每个主触点的选择性连接。 硅空间变压器安装在固定装置中，其提供与待测试的晶片或装置的弹性连接。 可以调整该夹具以使主触头与支撑探针卡板的平面平坦化。

公开(公告)号：US20060261827A1

公开(公告)日：2006-11-23

申请号：US11461734

申请日：2006-08-01

申请人： Timothy Cooper ,  Benjamin Eldridge ,  Carl Reynolds ,  Ravindra Shenoy

发明人： Timothy Cooper ,  Benjamin Eldridge ,  Carl Reynolds ,  Ravindra Shenoy

IPC分类号： G01R31/02

CPC分类号： G01R31/2887 ,  G01R3/00 ,  G01R31/2886

摘要： Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly.

摘要翻译： 公开了用于测试半导体器件的方法和装置。 相对于探针卡组件的探针，超行程停止限制要测试的设备的行程。 采用反馈控制技术来控制装置和探针卡组件的相对运动。 探针卡组件包括用于吸收相对于探针卡组件的待测试装置的过度行进的柔性基座。

公开(公告)号：US07128587B2

公开(公告)日：2006-10-31

申请号：US11264948

申请日：2005-11-01

申请人： Benjamin N. Eldridge ,  Carl V. Reynolds

发明人： Benjamin N. Eldridge ,  Carl V. Reynolds

IPC分类号： H01R13/44

CPC分类号： G01R31/2851 ,  G01R31/2886

摘要： The present invention discloses a cover over electrical contacts of a probe card used in testing die on a wafer. A testing machine is disclosed as having the covered probe card therein. Various mechanisms for uncovering the electrical contacts while it is located in the tester machine are disclosed.

公开(公告)号：US20060238211A1

公开(公告)日：2006-10-26

申请号：US11428423

申请日：2006-07-03

申请人： Benjamin Eldridge ,  Gary Grube ,  Ken Matsubayashi ,  Richard Larder ,  Makarand Shinde ,  Gaetan Mathieu

发明人： Benjamin Eldridge ,  Gary Grube ,  Ken Matsubayashi ,  Richard Larder ,  Makarand Shinde ,  Gaetan Mathieu

IPC分类号： G01R31/02

CPC分类号： G01R31/2891 ,  G01R1/07342 ,  G01R1/44 ,  G01R31/2886

摘要： The present invention discloses a method and system compensating for thermally induced motion of probe cards used in testing die on a wafer. A probe card incorporating temperature control devices to maintain a uniform temperature throughout the thickness of the probe card is disclosed. A probe card incorporating bi-material stiffening elements which respond to changes in temperature in such a way as to counteract thermally induced motion of the probe card is disclosed including rolling elements, slots and lubrication. Various means for allowing radial expansion of a probe card to prevent thermally induced motion of the probe card are also disclosed. A method for detecting thermally induced movement of the probe card and moving the wafer to compensate is also disclosed.

摘要翻译： 本发明公开了一种补偿晶片上测试晶片使用的探针卡的热诱导运动的方法和系统。 公开了一种结合温度控制装置的探针卡，以在探针卡的整个厚度上保持均匀的温度。 公开了一种包括双材料加强元件的探针卡，其包括滚动元件，狭槽和润滑，以响应于温度变化，以抵消探针卡的热诱导运动。 还公开了用于允许探针卡的径向膨胀以防止探针卡的热诱导运动的各种装置。 还公开了一种用于检测探针卡的热诱导运动并移动晶片进行补偿的方法。

公开(公告)号：US07119564B2

公开(公告)日：2006-10-10

申请号：US11216579

申请日：2005-08-30

申请人： Rod Martens ,  Benjamin N. Eldridge ,  Gary W. Grube ,  Ken S. Matsubayashi ,  Richard A. Larder ,  Makarand Shinde ,  Gaetan L. Mathieu

发明人： Rod Martens ,  Benjamin N. Eldridge ,  Gary W. Grube ,  Ken S. Matsubayashi ,  Richard A. Larder ,  Makarand Shinde ,  Gaetan L. Mathieu

IPC分类号： G01R31/02

CPC分类号： G01R31/2891 ,  G01R1/07342 ,  G01R31/2886

摘要： The present invention discloses a method and system compensating for thermally induced motion of probe cards used in testing die on a wafer. A probe card incorporating temperature control devices to maintain a uniform temperature throughout the thickness of the probe card is disclosed. A probe card incorporating bi-material stiffening elements which respond to changes in temperature in such a way as to counteract thermally induced motion of the probe card is disclosed including rolling elements, slots and lubrication. Various means for allowing radial expansion of a probe card to prevent thermally induced motion of the probe card are also disclosed. A method for detecting thermally induced movement of the probe card and moving the wafer to compensate is also disclosed.

公开(公告)号：US07116119B2

公开(公告)日：2006-10-03

申请号：US11059164

申请日：2005-02-15

申请人： Alistair Nicholas Sporck ,  Makarand S. Shinde

发明人： Alistair Nicholas Sporck ,  Makarand S. Shinde

IPC分类号： G01R31/02

CPC分类号： G01R1/07342

摘要： A probe card assembly includes a printed circuit board with tester contacts for making electrical connections to a semiconductor tester. The probe card assembly also includes a probe head assembly with probes for contacting a semiconductor device under test. One or more daughter cards is mounted to the printed circuit board such that they are substantially coplanar with the printed circuit board. The daughter cards may contain a circuit for processing test data, including test signals to be input into the semiconductor and/or response signals generated by the semiconductor device in response to the test signals.

公开(公告)号：US07108546B2

公开(公告)日：2006-09-19

申请号：US09886521

申请日：2001-06-20

申请人： Charles A. Miller ,  Benjamin N. Eldridge

发明人： Charles A. Miller ,  Benjamin N. Eldridge

IPC分类号： H01R9/05

CPC分类号： G01R1/0466 ,  H01R13/025 ,  H01R13/40 ,  H01R2201/20

摘要： An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through respective ones of a plurality of through holes of a body of the interface; an interconnection component comprising a first plurality of contact points aligned with respective ones of conductors of the plurality of cables and a second plurality of contact points aligned to corresponding contact points of a device to be tested. Also, a method of routing signals through the conductors of the plurality of cables between electronic components.