公开(公告)号：US20060199390A1

公开(公告)日：2006-09-07

申请号：US11369448

申请日：2006-03-06

Applicant: George Dudnikov ,  Franz Gisin

Inventor： George Dudnikov ,  Franz Gisin

IPC: H01L21/311 ,  H01L23/48

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Abstract translation: 公开了通过在PCB堆叠中使用电镀抗蚀剂将多个通孔结构同时分隔成电隔离部分的系统和方法。 通过在子复合结构中的一个或多个位置选择性地沉积电镀抗蚀剂来制造这种通孔结构。 具有在不同位置沉积的电镀抗蚀剂的多个亚复合结构层压以形成期望的PCB设计的PCB堆叠。 通过导电层，电介质层和电镀抗蚀剂在PCB堆叠中钻出通孔。 因此，PCB面板具有多个通孔，然后可以通过将PCB面板放置在种子池中，然后浸入无电解铜浴中而同时进行电镀。 这种分隔的通孔增加布线密度并限制通孔结构中的短截线形成。 这种分隔的通孔允许多个电信号穿过每个电隔离部分而没有彼此的干扰。

公开(公告)号：US20060061925A1

公开(公告)日：2006-03-23

申请号：US10944124

申请日：2004-09-17

Applicant: Karen Shrier

Inventor： Karen Shrier

IPC: H02H9/00

CPC classification number: H05K1/0256 ,  H01C7/10 ,  H01C7/13 ,  H01C7/18 ,  H01L2224/48091 ,  H01L2924/00014 ,  H05K1/0259 ,  H05K1/167 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/0738 ,  H01L2224/45099

Abstract: A device (10) for suppressing electrostatic discharge comprises first and second multilayer structures (14, 16) surrounding an electrostatic discharge reactance layer (12), the resistance of said electrostatic discharge reactance layer (12) varying in response to the occurrence of an electrostatic discharge signal. Each multilayer structure (14, 16) comprises a barrier layer (18), a terminal layer (20) and an electrode layer (28). Alternatively, a conductive layer (80) can be used instead of a second multilayer structure (16). An ESD suppression device (110) can be embedded in a printed circuit board (122, 210) providing a way to protect board components from harmful ESD events.

Abstract translation: 用于抑制静电放电的装置（10）包括围绕静电放电电抗层（12）的第一和第二多层结构（14,16），所述静电放电电抗层（12）的电阻响应于静电发生而变化 放电信号。 每个多层结构（14,16）包括阻挡层（18），端子层（20）和电极层（28）。 或者，可以使用导电层（80）代替第二多层结构（16）。 ESD抑制装置（110）可嵌入印刷电路板（122,210）中，从而提供保护电路板部件免受有害ESD事件的影响。

公开(公告)号：US06935879B2

公开(公告)日：2005-08-30

申请号：US10192288

申请日：2002-07-10

Applicant: Stephen J. Whitney ,  David Perry

Inventor： Stephen J. Whitney ,  David Perry

IPC: H01R12/00 ,  H01R13/66 ,  H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  H05K7/10 ,  H05K9/00 ,  H01R13/53 ,  H01C7/10

CPC classification number: H05K1/0259 ,  H01R12/592 ,  H01R13/6666 ,  H01R24/62 ,  H05K1/167 ,  H05K1/18 ,  H05K7/1092 ,  H05K9/0067 ,  H05K2201/0738 ,  H05K2201/10189 ,  H05K2201/10325

Abstract: The present invention provides connectors having circuit protection. Specifically, the present invention provides a device that operates with existing or new connectors to provide overvoltage protection to same. The device includes a strip of conductive material along which voltage variable material (“VVM”) is applied. The strip also includes an exposed portion not having the VVM deposition. The VVM contacts a plurality of signal conductors of the connector. The exposed portion contacts at least one ground conductor of the connector. When an overvoltage condition occurs along one of the signal conductors, the VVM switches from a high impedance to a low impedance state, allowing the transient threat to dissipate, at least in part, to one or more ground conductor.

Abstract translation: 本发明提供具有电路保护的连接器。 具体地说，本发明提供了一种使用现有的或新的连接器进行操作以向其提供过电压保护的装置。 该装置包括一根导电材料条，其上施加有电压可变材料（“VVM”）。 条带还包括不具有VVM沉积的暴露部分。 VVM接触连接器的多个信号导体。 暴露部分接触连接器的至少一个接地导体。 当沿着信号导体之一发生过电压状态时，VVM从高阻抗切换到低阻抗状态，允许瞬态威胁至少部分地消散到一个或多个接地导体。

公开(公告)号：US06797145B2

公开(公告)日：2004-09-28

申请号：US10315496

申请日：2002-12-09

Applicant: Lex Kosowsky

Inventor： Lex Kosowsky

IPC: C25D548

CPC classification number: H05K1/0254 ,  C25D5/54 ,  H05K1/0373 ,  H05K1/167 ,  H05K3/188 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0215 ,  H05K2201/0738 ,  H05K2203/105 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: An electrochemical processing method is provided for forming a current carrying device for semiconductor chip packaging and similar applications. The method comprises selecting sections of a substrate to carry current wherein a selected section is at least partly covered with a voltage switchable dielectric material, rendering the voltage switchable dielectric material conductive, and electrochemically forming a current carrying material directly on the voltage switchable dielectric material. The voltage switchable dielectric material can have a characteristic voltage, such that when a voltage having a magnitude exceeding the characteristic voltage is applied to the voltage switchable dielectric material, the voltage switchable dielectric material switches from a dielectric material to a conductive material. When conductive, the voltage switchable dielectric material is amenable to electrochemical processing such as electroplating.

Abstract translation: 提供一种用于形成用于半导体芯片封装的载流装置和类似应用的电化学处理方法。 该方法包括选择衬底的部分以承载电流，其中所选择的部分至少部分地被可开关电介质材料覆盖，使得电压可切换电介质材料导电，并且电化学地在可开关电介质材料上直接形成载流材料​​。 电压可切换介电材料可以具有特征电压，使得当具有超过特征电压的电压的电压被施加到可开关电介质材料时，可切换电介质材料从电介质材料切换到导电材料。 导电时，电压可切换介电材料适用于诸如电镀的电化学处理。

公开(公告)号：US20030071245A1

公开(公告)日：2003-04-17

申请号：US09976964

申请日：2001-10-11

Inventor： Edwin James Harris IV

IPC: H05K001/03 ,  H05K001/09 ,  H01B001/00 ,  H01C001/00

CPC classification number: H01C7/12 ,  H01C7/027 ,  H01C7/105 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0373 ,  H05K1/167 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0323 ,  H05K2201/0329 ,  H05K2201/0738 ,  Y10S428/901 ,  Y10T29/49124 ,  Y10T29/49172

Abstract: The present invention provides an improved voltage variable material (nullVVMnull). More specifically, the present invention provides an improved printed circuit board substrate, an improved device having circuit protection an improved data communications cable having circuit protection and a method for mass producing devices employing the VVM substrate of the present invention. The VVM substrate eliminates the need for an intermediate daughter or carrier board by impregnating conductive particles and possibly semiconductive and/or insulative particles associated with known volatage variable materials into the varnish or epoxy resin associated with known printed circuit board substrates.

Abstract translation: 本发明提供一种改进的电压可变材料（“VVM”）。 更具体地，本发明提供一种改进的印刷电路板基板，具有电路保护的改进的装置，具有电路保护的改进的数据通信电缆以及使用本发明的VVM基板的批量生产装置的方法。 VVM基板通过将与已知的挥发性可变材料相关联的导电颗粒和可能的半导体和/或绝缘颗粒浸渍到与已知印刷电路板基底相关联的清漆或环氧树脂中而不需要中间子体或载体板。

公开(公告)号：US20160379738A1

公开(公告)日：2016-12-29

申请号：US15101650

申请日：2014-12-05

Applicant: HITACHI METALS, LTD.

Inventor： Naoyuki OKAMOTO ,  Hiroyuki ITO ,  Toshiki KIDA

IPC: H01C7/112 ,  H01C17/30 ,  B32B18/00 ,  H01C1/14 ,  C04B35/453 ,  C04B35/64 ,  H05K1/02 ,  H01C17/065

CPC classification number: H01C7/112 ,  B32B18/00 ,  B32B2307/206 ,  B32B2457/00 ,  C04B35/453 ,  C04B35/64 ,  C04B2235/3215 ,  C04B2235/3224 ,  C04B2235/3241 ,  C04B2235/3262 ,  C04B2235/3263 ,  C04B2235/3275 ,  C04B2235/3277 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/3409 ,  C04B2235/656 ,  C04B2235/72 ,  C04B2237/34 ,  C04B2237/62 ,  H01C1/14 ,  H01C17/06546 ,  H01C17/30 ,  H05K1/0254 ,  H05K2201/0738

Abstract: To provide a zinc oxide-based varistor that exhibits adequate characteristics without using antimony. Disclosed is a sintered body for a varistor, including zinc oxide as a main component; 0.6 to 3.0 mol % of bismuth oxide in terms of bismuth (Bi); 0.2 to 1.4 mol % of cobalt oxide in terms of cobalt (Co); 0.1 to 1.5 mol % of chrome oxide in terms of chrome (Cr); and 0.1 to 1.5 mol % of manganese oxide in terms of manganese (Mn), wherein the contents of antimony (Sb), a rare earth element and tin (Sn) are not more than a level of impurities.

Abstract translation: 提供在不使用锑的情况下表现出足够特性的氧化锌基压敏电阻。 公开了一种用于变阻器的烧结体，包括氧化锌作为主要成分; 铋（Bi）为0.6〜3.0摩尔％的氧化铋。 以钴（Co）计为0.2〜1.4摩尔％的氧化钴; 以铬（Cr）计为0.1〜1.5摩尔％的氧化铬; 和0.1〜1.5摩尔％的以锰（Mn）计的氧化锰，其中锑（Sb），稀土元素和锡（Sn）的含量不大于杂质含量。

公开(公告)号：US09084354B2

公开(公告)日：2015-07-14

申请号：US13597152

申请日：2012-08-28

Applicant: Robert Fleming ,  Lex Kosowsky ,  Shurui Shang ,  Bhret Graydon ,  Xiaofeng Chen ,  Glen Irvin

Inventor： Robert Fleming ,  Lex Kosowsky ,  Shurui Shang ,  Bhret Graydon ,  Xiaofeng Chen ,  Glen Irvin

IPC: H05K3/10 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/0259 ,  H05K1/0271 ,  H05K1/036 ,  H05K1/0373 ,  H05K3/0005 ,  H05K2201/068 ,  H05K2201/0738 ,  H05K2201/09136 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T156/10

Abstract: A method for designing a printed circuit board to meet a specification is described. A first voltage switchable dielectric material is placed in apposition with a first copper foil. A second voltage switchable dielectric material is placed in apposition with a second copper foil. An arcuate portion of the first copper foil is placed in apposition with a first side of an aluminum member, an adhesive substance being situated between the first copper foil and the first side of the aluminum member. An arcuate portion of the second copper foil in is placed apposition with a second side of the aluminum member, an adhesive substance being situated between the second copper foil and the second side of the aluminum member.

Abstract translation: 描述了一种用于设计符合规格的印刷电路板的方法。 第一电压可切换电介质材料与第一铜箔一起放置。 第二可电压切换电介质材料与第二铜箔一起放置。 第一铜箔的弓形部分与铝构件的第一侧相配合，粘合剂物质位于第一铜箔和铝构件的第一侧之间。 第二铜箔的弧形部分与铝构件的第二侧配合，粘合剂物质位于第二铜箔和铝构件的第二侧之间。

公开(公告)号：US09007165B2

公开(公告)日：2015-04-14

申请号：US13524776

申请日：2012-06-15

Applicant: Lex Kosowsky ,  Robert Fleming ,  Bhret Graydon

Inventor： Lex Kosowsky ,  Robert Fleming ,  Bhret Graydon

IPC: H01C7/10 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0257 ,  H05K1/0259 ,  H05K1/0373 ,  H05K2201/0738 ,  H05K2203/105

Abstract: A substrate device includes an embedded layer of VSD material that overlays a conductive element or layer to provide a ground. An electrode, connected to circuit elements that are to be protected, extends into the thickness of the substrate to make contact with the VSD layer. When the circuit elements are operated under normal voltages, the VSD layer is dielectric and not connected to ground. When a transient electrical event occurs on the circuit elements, the VSD layer switches instantly to a conductive state, so that the first electrode is connected to ground.

Abstract translation: 衬底器件包括覆盖导电元件或层以提供接地的VSD材料的嵌入层。 连接到要被保护的电路元件的电极延伸到衬底的厚度以与VSD层接触。 当电路元件在正常电压下工作时，VSD层是电介质的，不连接到地。 当在电路元件上发生瞬态电事件时，VSD层立即切换到导通状态，使得第一电极连接到地。

公开(公告)号：US08940193B2

公开(公告)日：2015-01-27

申请号：US13158356

申请日：2011-06-10

Applicant: Lex Kosowsky ,  Robert Fleming

Inventor： Lex Kosowsky ,  Robert Fleming

IPC: H01B1/06 ,  H01B1/12 ,  H01C7/10 ,  B05D5/12 ,  B82Y10/00 ,  H01B1/22 ,  H01B1/24 ,  H01C7/105 ,  H01C17/065 ,  H05K1/02 ,  H05K3/18 ,  H05K1/03 ,  H05K1/16

CPC classification number: H01C7/1006 ,  B82Y10/00 ,  H01B1/22 ,  H01B1/24 ,  H01C7/105 ,  H01C17/0652 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0373 ,  H05K1/167 ,  H05K3/188 ,  H05K2201/0248 ,  H05K2201/0257 ,  H05K2201/026 ,  H05K2201/0272 ,  H05K2201/0738 ,  H05K2203/0723 ,  H05K2203/105 ,  Y10S977/742 ,  Y10S977/779 ,  Y10T428/30 ,  Y10T428/31678

Abstract: One or more embodiments provide for a device that utilizes voltage switchable dielectric material having semi-conductive or conductive materials that have a relatively high aspect ratio for purpose of enhancing mechanical and electrical characteristics of the VSD material on the device.

Abstract translation: 一个或多个实施例提供了一种使用具有半导体或导电材料的电压可切换介电材料的器件，该器件具有相对较高的纵横比，以便增强器件上的VSD材料的机械和电学特性。

公开(公告)号：US20130194708A1

公开(公告)日：2013-08-01

申请号：US13361504

申请日：2012-01-30

Applicant: Thomas Lövskog ,  Jonny Strandh

Inventor： Thomas Lövskog ,  Jonny Strandh

IPC: H02H9/04 ,  H05K3/10

CPC classification number: H05K1/026 ,  H01C7/1006 ,  H01C7/12 ,  H01T4/08 ,  H05K1/167 ,  H05K3/027 ,  H05K2201/0738 ,  H05K2203/0315 ,  H05K2203/107 ,  Y10T29/49155

Abstract: A method is provided for forming a current carrying structure with improved electrostatic discharge protection. The current carrying structure includes a conductive material layer and a voltage switchable dielectric layer adapted to switch between insulative and conductive at a predetermined voltage between the ground plane and the conductive material. An aperture is formed through the voltage switchable dielectric layer, and conductive material is deposited in the aperture to form a conductive pathway between the voltage switchable dielectric layer and another layer. A spark gap is created between the conductive material of the aperture and a ground portion using a laser to remove a portion of the conductive material layer from an area surrounding the aperture without substantially modifying physical properties of the underlying switchable dielectric layer.

Abstract translation: 提供一种用于形成具有改进的静电放电保护的载流结构的方法。 载流结构包括导电材料层和适于在接地平面和导电材料之间的预定电压下在绝缘和导电之间切换的电压可切换电介质层。 通过可切换电介质层形成孔径，并且导电材料沉积在孔中以在可切换电介质层与另一层之间形成导电通路。 在孔的导电材料和使用激光的接地部分之间产生火花间隙，以从导电材料层的一部分周围去除一部分，而不会基本上改变下面的可切换电介质层的物理特性。