公开(公告)号：US07786596B2

公开(公告)日：2010-08-31

申请号：US12038501

申请日：2008-02-27

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L23/48

CPC classification number: H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

公开(公告)号：US07741231B2

公开(公告)日：2010-06-22

申请号：US12056773

申请日：2008-03-27

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/31

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US20100025857A1

公开(公告)日：2010-02-04

申请号：US12181467

申请日：2008-07-29

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L23/48 ,  G06F9/45

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684

Abstract: An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.

Abstract translation: 具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

公开(公告)号：US20090315188A1

公开(公告)日：2009-12-24

申请号：US12550494

申请日：2009-08-31

Applicant: Brent Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Brent Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L23/488 ,  H01L23/48

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.

Abstract translation: 提供绝缘体上硅（SOI）结构，用于在硅晶片载体结构中形成通孔，而无需背面光刻。 SOI结构包括用一层掩埋氧化物结合到硅衬底结构的硅晶片载体结构和分离这些硅结构的氮化物层。 在硅载体结构中形成通孔，并且通过氧化物层到达氮化物层，并且通孔的壁被钝化。 通孔填充有多晶硅或导电材料的填充材料。 然后将衬底结构回蚀刻到氮化物层，氮化物层被回蚀刻到填充材料上。 当填充材料是多晶硅时，多晶硅被蚀刻掉，形成开口通孔到载体晶片结构的顶表面。 然后通孔用导电材料回填。

公开(公告)号：US20090140404A1

公开(公告)日：2009-06-04

申请号：US12038501

申请日：2008-02-27

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L23/10

CPC classification number: H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract translation: 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

公开(公告)号：US07521798B2

公开(公告)日：2009-04-21

申请号：US11943277

申请日：2007-11-20

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07488680B2

公开(公告)日：2009-02-10

申请号：US11214602

申请日：2005-08-30

Applicant: Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/4763

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

Abstract translation: 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：US20090032920A1

公开(公告)日：2009-02-05

申请号：US12167745

申请日：2008-07-03

Applicant: Leena P. Buchwalter ,  Paul S. Andry ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

Inventor： Leena P. Buchwalter ,  Paul S. Andry ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L21/67092 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10S414/139 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract translation: 提供了用于避免载波边缘破裂的集成电路模块的激光释放和玻璃切屑去除工艺。

公开(公告)号：US20080179755A1

公开(公告)日：2008-07-31

申请号：US11669924

申请日：2007-01-31

Applicant: Paul S. Andry ,  L. Paivikki Buchwalter ,  Anurag Jain ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Michelle L. Steen ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  L. Paivikki Buchwalter ,  Anurag Jain ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Michelle L. Steen ,  Cornelia K. Tsang

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

Abstract translation: 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

公开(公告)号：US20080142958A1

公开(公告)日：2008-06-19

申请号：US12026776

申请日：2008-02-06

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornella K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornella K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L23/02

CPC classification number: H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.